Semiconductor Packaging

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Monolithic scaling limitations drive the growth of 2.5/3D multi-chiplet, heterogeneous integration that enables PPA targets to be met. Our integrated flow addresses prototyping challenges to signoff for FOWLP, 2.5/3D IC, and other emerging integration technologies.

Learn more about semiconductor packaging design and verification.

Featured posts

Illustration of 3D IC stacked design

3D IC technology: your comprehensive guide to enabling heterogeneous integration

May 19, 2025

What is 3D IC technology? 3D IC technology refers to the integration of multiple silicon dies or wafers in a…

By John McMillan
14 MIN READ
Screen shots of Innovator3D IC software in use.

Exploring TSMC InFO_oS and InFO_PoP certification

February 28, 2025

Siemens EDA has recently achieved this certification for Xpedition Package Designer as part of the TSMC InFO_oS and InFO_PoP workflows.

By Keith Felton
2 MIN READ
Text that says what's new in IC Packaging 2409 next to a stylized X

What’s new in IC Packaging 2409

September 19, 2024

The 2409 release is a landmark update in the field of electronic design automation (EDA), introducing a next-generation solution for…

By Keith Felton
3 MIN READ

Latest posts

System-level, post-layout electrical analysis for high-density advanced packaging (HDAP)

December 18, 2023

HDAP designs like FOWLP need post-layout simulation (analog) and post-layout STA (digital) flows to augment basic physical verification DRC and LVS.

By John McMillan
3 MIN READ

Crossing the chasm: Bringing SoC and package verification together

December 8, 2023

3D IC package designers need assembly-level LVS for HDAP verification.

By John McMillan
2 MIN READ

Package designers need assembly-level LVS for HDAP verification

December 5, 2023

While advanced integrated circuit (IC) packaging is a fast-growing market, comprehensive package verification still has a ways to go. Unique…

By John McMillan
2 MIN READ
An image of an IC package design in Xpedition Package Designer with text that says: Achieving substrate supplier fabrication requirements: a designer's guide

Achieving substrate supplier fabrication requirements: a designer’s guide

December 5, 2023

Designing advanced package layouts with large areas of metal can be a daunting task, given the stringent requirements imposed by…

By Keith Felton
3 MIN READ

Understanding 3D IC Technology: Unveiling the Future of Integrated Circuits

November 6, 2023

Delve into the world of 3D IC technology, its architecture, benefits, and applications. Learn how it’s reshaping the future of integrated circuits for enhanced performance and efficiency.

By John McMillan
6 MIN READ
Image of chiplets with text onscreen saying HBM

High Bandwidth Memory (HBM): Unleashing the power of next-gen memory technology

September 28, 2023

In the ever-evolving realm of semiconductor technology, one innovation stands out above the rest: High Bandwidth Memory (HBM). Offering unparalleled…

By Edward Hudson
3 MIN READ
What's new in Xpedition IC Packaging

What’s new in Xpedition IC Packaging VX.2.14

September 19, 2023

The new VX.2.14 release of Xpedition IC Packaging includes improvements and enhancements to both Xpedition Substrate Integrator and Xpedition Package…

By Keith Felton
2 MIN READ

SemiWiki Podcast – An expert panel discussion on the move to chiplets

September 13, 2023

Listen in as Tony Mastroianni Advanced Packaging Solutions Director – Siemens EDA along with Saif Alam Vice President of Engineering…

By John McMillan
< 1 MIN READ
system technology co-optimization

Shifting left with system technology co-optimization for IC packaging

August 17, 2023

We have witnessed and learned about the industry’s significant shift in semiconductors. The traditional approach of transistor scaling, once universally…

By Keith Felton
3 MIN READ