Prashant Seetharaman
Article Roundup: Open letter to the IC Design community, Automating Failure Mode Analysis For Automotive Safety, Get To Know DDRx, SerDes, and PDN, A hypervisor on a multicore system, Knowledge is Power – Introducing Mentor AMS Webinar Series

Article Roundup: Open letter to the IC Design community, Automating Failure Mode Analysis For Automotive Safety, Get To Know DDRx, SerDes, and PDN, A hypervisor on a multicore system, Knowledge is Power – Introducing Mentor AMS Webinar Series

June 5, 2020

Open letter to the IC design community Automating Failure Mode Analysis For Automotive Safety Get To Know DDRx, SerDes, and…

By Expert Insights
3 MIN READ
Article Roundup: Joe Sawicki on DFT and life-cycle management, Aging Analysis Standard Solidifies Through Collaborative Effort, Mentor Masterclass on ML SoC Design, Staying True to the Mission to Fight COVID-19, Hardware Emulation Future is Exciting

Article Roundup: Joe Sawicki on DFT and life-cycle management, Aging Analysis Standard Solidifies Through Collaborative Effort, Mentor Masterclass on ML SoC Design, Staying True to the Mission to Fight COVID-19, Hardware Emulation Future is Exciting

May 28, 2020

Joe Sawicki on DFT and life-cycle management Aging Analysis Standard Solidifies Through Collaborative Effort Mentor Masterclass on ML SoC Design…

By Expert Insights
3 MIN READ
Article Roundup: How MaxLinear got faster signoff DRC while optimizing reliability and manufacturability, HLS Powers AI Revolution, Earlier is Better in Latch-Up Detection, Embedding Software Algorithms in New Chip Applications Calls for New Verification, Improving Circuit Reliability

Article Roundup: How MaxLinear got faster signoff DRC while optimizing reliability and manufacturability, HLS Powers AI Revolution, Earlier is Better in Latch-Up Detection, Embedding Software Algorithms in New Chip Applications Calls for New Verification, Improving Circuit Reliability

May 15, 2020

How MaxLinear got faster signoff DRC while optimizing reliability and manufacturability HLS Powers AI Revolution Earlier Is Better In Latch-Up…

By Expert Insights
3 MIN READ
Article Roundup: DvConUS Edition of Verification Horizons is Out, Why is PSS is Important?, Challenges and Opportunities with Medical Embedded Applications, 5G needs cohesive pre- and post-silicon verification, A Conversation with Wally Rhines: Predicting Semiconductor Business Trends After Moore’s Law

Article Roundup: DvConUS Edition of Verification Horizons is Out, Why is PSS is Important?, Challenges and Opportunities with Medical Embedded Applications, 5G needs cohesive pre- and post-silicon verification, A Conversation with Wally Rhines: Predicting Semiconductor Business Trends After Moore’s Law

April 23, 2020

DVConUS Edition of Verification Horizons is Out! Why Is PSS So Important? Challenges and Opportunities with Medical Embedded Applications 5G…

By Expert Insights
3 MIN READ
Article Roundup: Training novel NVM non determinism, High Level Synthesis at the Edge, The ABCs of Functional Verification, Improving functional safety for ICs , Tessent awarded by Samsung, Tessent awarded by Samsung, Interview with Mentor’s Sagi Reuven: Business Practices Drive the Smart Factory, Not the Other Way Around.

Article Roundup: Training novel NVM non determinism, High Level Synthesis at the Edge, The ABCs of Functional Verification, Improving functional safety for ICs , Tessent awarded by Samsung, Tessent awarded by Samsung, Interview with Mentor’s Sagi Reuven: Business Practices Drive the Smart Factory, Not the Other Way Around.

April 8, 2020

Taming novel NVM non determinism High Level Synthesis at the Edge Improving Functional Safety for ICs Tessent awarded by Samsung…

By Expert Insights
3 MIN READ
Article Roundup: EDA In the Cloud, How to Become an RTL Simulation Expert vs Hardware Emulation Expert, Multicore systems: heterogeneous architectures – untangling the technology and terminology, Earlier is Better In Latch-Up Detection, Right-first-time PCB layout for spacecraft avionics

Article Roundup: EDA In the Cloud, How to Become an RTL Simulation Expert vs Hardware Emulation Expert, Multicore systems: heterogeneous architectures – untangling the technology and terminology, Earlier is Better In Latch-Up Detection, Right-first-time PCB layout for spacecraft avionics

March 5, 2020

How to Become an RTL Simulation Expert vs. Hardware Emulation Expert Multicore systems: heterogeneous architectures – untangling the technology and…

By Expert Insights
3 MIN READ
Article Roundup: The ABCs of Functional Verification, Where are we with HDAP LVS verification?, Reducing Power at the RTL Level, An Optimal Path to DFT Automation, Embedded World 2020

Article Roundup: The ABCs of Functional Verification, Where are we with HDAP LVS verification?, Reducing Power at the RTL Level, An Optimal Path to DFT Automation, Embedded World 2020

February 26, 2020

The ABCs of functional verification techniques Where are we with HDAP LVS verification? Reducing Power At The RTL Level  An…

By Expert Insights
3 MIN READ
Article Roundup: AI Rewrites the Possibilities of Digital Twin, Automotive Industry On Course To Disruption & Evolution, Choosing an Embedded Operating System, Mythic takes Analog FASTSPICE and Symphony from Mentor for AI Design, Siemens on Challenges and Trends in the Electronics Industry

Article Roundup: AI Rewrites the Possibilities of Digital Twin, Automotive Industry On Course To Disruption & Evolution, Choosing an Embedded Operating System, Mythic takes Analog FASTSPICE and Symphony from Mentor for AI Design, Siemens on Challenges and Trends in the Electronics Industry

February 19, 2020

AI Rewrites the Possibilities of Digital Twin Automotive Industry On Course To Disruption And Evolution Choosing an embedded operating system…

By Expert Insights
3 MIN READ
Article Roundup: Catch latch-up earlier with schematic topology-based analysis, Toward more efficient formal strategies for deadlock, Balancing Flexibility and quality in SRAM Verification, It’s The Small Stuff That Gets You…, Clock-domain crossing protocols: an automated formal-to-simulation flow

Article Roundup: Catch latch-up earlier with schematic topology-based analysis, Toward more efficient formal strategies for deadlock, Balancing Flexibility and quality in SRAM Verification, It’s The Small Stuff That Gets You…, Clock-domain crossing protocols: an automated formal-to-simulation flow

February 19, 2020

Catch latch-up earlier with schematic topology-based analysis Toward more efficient formal strategies for deadlock Balancing Flexibility And Quality In SRAM…

By Expert Insights
3 MIN READ