- How to achieve accurate reset domain crossing verification
- Enhancing vehicle design and simulation
- Turns Complexity into a Competitive Advantage with Digital Twin and Simulation
- Balancing PPA as machine learning moves to the edge
- MIM/MOM capacitor extraction boosts analog and RF designs
How to achieve accurate reset domain crossing verification
This article describes the methodology for accurate RDC verification based on a hierarchical data model (HDM) approach. It details a novel approach that in part satisfies the requirements of this methodology by using a portable data model that captures and stores all the information required for SoC RDC verification. The HDM encapsulates the RDC intent of the block, which can be seamlessly integrated across SoCs, providing accurate verification and debugging capabilities and leading to faster RDC verification closure.
Enhancing vehicle design and simulation
This blog focuses on the role of AI in generative design and simulation of AI chips to enhance vehicle design. Generative design relies on AI algorithms to find an optimal solution by systematic variation of parameters, structure or shape of a design. AI technologies are beneficial to designers that build digital twin models with machine learning that can compare “learned” behavior against simulation models and more.
The digital twin is a virtual representation of the product and the manufacturing process, thereby covering the entire lifecycle. It is enriched over time by analyzing data coming from machines in the manufacturing process or the product being used out in the field. By feeding these insights back into the development process, one can improve the fidelity of such a digital twin, which is referred to as the comprehensive digital twin. It is used to predict behavior, optimize performance and validate the most complex products and processes. In this article, Dr. Jan Leuridan, Senior Vice President, Simulation and Test Solutions, highlights the need for companies to utilize digitalization solutions and more.
Balancing PPA as machine learning moves to the edge
The progression of ML algorithms running on edge devices has spurred an explosion in hardware architectures optimized for power, performance, and area (PPA). Catapult® HLS provides hardware designers with the ability to rapidly create and verify complex hardware architectures using C++/SystemC. This article explains how HLS is a better enabler for multi-architecture projects in terms of both design and verification.
This article talks about the desirable characteristics of MIM/MOM capacitors and how they are widely used in anlalog/RF designs. Designers typically require a combination of both rule-based and field-solver-based extraction, as well as context aware functionality, to ensure designers can obtain accurate results in a timely manner. The authors explain in detail about PEX at the block level, parasitic effects inside the device region and more.