Mentor at DAC 2020 : A Virtual Experience

Mentor, a Siemens Business is a Platinum Sponsor for this year’s Design Automation Conference (DAC). The 57th Design Automation Conference (DAC) executive committee, together with ACM and IEEE, have decided to move DAC 2020 to a virtual event format scheduled for July 20 – 24, 2020.

The Design Automation Conference (DAC) is recognized as the premier conference for design and automation of electronic systems. DAC offers outstanding training, education, exhibits and superb networking opportunities for designers, researchers, tool developers and vendors.

 

CONFERENCE PROGRAM SCHEDULE

  • Monday:
  1. Continuing Evolution of the Electronics Ecosystem

Monday July 20, 11:00am – 11:45am | DAC Pavilion

Speaker:  Wally Rhines – Mentor, A Siemens Business

In this session, Dr. Rhines will provide an update on the electronics industry and discuss future directions for EDA.  He will also throw light on systems companies including automotive, aerospace and data center companies, and how they have continued their move into the world of IC design.

  1. Easy Deadlock Verification and Debug with Advanced Formal Verification

Monday July 20, 01:30pm -03:00pm | Designer Track Paper Presentation | *Best Paper Nominee

Authors: Joe Hupcey III – ICVS Product Manager, Mentor, A Siemens Business | Jeremy Levitt – Principal Enginer – ICVS, Mentor, A Siemens Business

This presentation will throw light on how formal and static methods continue to be a critical and growing part of verification. The first half of this session will present new techniques in this area for deadlock verification, finite state machine checks, and reset domain crossing (RDC) challenges. The second half of this session will present some new ideas for effective UVM-based simulation.

 

  • Tuesday:
  1. Advanced Power Techniques/RISC-V Design and Validation

Tuesday July 21, 01:30pm – 03:00pm | Designer Track Presentation

Chair: Dave Rich – Product Manager, ICVS – Mentor, A Siemens Business

Power consumption continues to be a critical issue in any modern design. The first half of this session will present a variety of new techniques related to low-power design and validation. Another topic that has taken the industry by storm in recent years is the revolutionary open-source RISC-V ISA. In the second half of this session, we will discuss some new ideas in design and validation related to this architecture.

 

2. Silicon Bug Hunt with “Deep Sea Fishing” Formal Verification Methodology

Tuesday July 21, 07:30am – 08:30am| Designer Track Poster Presentation

Speaker: Ping YeungMentor, A Siemens Business
Presenters: Ping YeungMentor, A Siemens Business, Joe Hupcey III – ICVS Product Manager, Mentor, A Siemens Business

 

3. Considering Both Power and Clock Designs: A Method For Successful Verification of Power Domain-Aware Clock Domain Crossings

Tuesday July 21, 07:30am – 08:30am| Designer Track Poster Presentation

Author:  Kurt TakaraMentor, A Siemens Business, Fremont CA

 

4. Effective High-Level Synthesis Flow for ISP Hardware Design Performance and Area Optimization

Tuesday July 21, 07:30am – 08:30am| Designer Track Poster Presentation

Speaker: William Lee Mentor, A Siemens Business, Seongnam, Republic of Korea
Author: William Lee Mentor, A Siemens Business, Seongnam, Republic of Korea

5. Functional Safety Island – As Easy as Palm Trees and Cocktails

Tuesday July 21, 07:30am – 08:30am| Designer Track Poster Presentation

Speaker: Lee C. Harrison – Mentor, A Siemens Business, United Kingdom
Author: Lee C. Harrison – Mentor, A Siemens Business, United Kingdom

 

6. Accelerating Early Design Physical Verification Cycle

Tuesday July 21, 07:30am – 08:30am| Designer Track Poster Presentation

Authors: Nermeen Hossan Mentor, A Siemens Business, Egypt | Bhavani Prasad – Mentor, A Siemens Business, Bangalore, India

 

7. Improving Transition-Coverage Cycle Time with a Declarative Description

Tuesday July 21, 07:30am – 08:30am| Designer Track Poster Presentation

Authors: Ammar AhmadMentor, A Siemens Business | Matthew Ballance, Mentor, A Siemens Business

 

8. Cross Products Hotspot Detection with Calibre SONR: A Machine Learning Technique

Tuesday July 21, 07:30am – 08:30am| Designer Track Poster Presentation

Authors: Yuansheng Ma, Juli Optiz, Rui Wu, Le Hong, Liang Cao, Dingyi Hong, Joerg Mellmann, Yuyang Sun, James WordMentor, A Siemens Business

 

9. Rapid Adoption of Full-Chip Hierarchical CDC Analysis

Tuesday July 21, 07:30am – 08:30am| Designer Track Poster Presentation

Authors: Kurt TakaraMentor, A Siemens Business

 

 

  • Wednesday:
  1. How to Train Your Dragon Before You Have Machine Learning Training Data – A Litho Hotspot Validation Solution

Wednesday, July 22, 3:30pm – 5:00pm | Designer Track Paper Presentation

Speaker: Joe Kwan, Product Marketing Manager, Mentor, A Siemens Business
Authors: Joe Kwan, Wael Elmanhawy, Aliaa Kabeel, Sarah Rizk, Mohamed Ismail, Kareem Madkour  – Mentor, A Siemens Business

 

  • Thursday:
  1. High-Level Synthesis 1974 – 2020: The Meteoric Rise of a Hot Topic?

Thursday, July 23, 3:30pm – 4:30pm | Panel

Panelist: Bryan Bowyer – Mentor, A Siemens Business

This panel celebrates the success of high-level synthesis as an important tool in CAD. High-level synthesis originated with research in the 1970s; a steady stream of innovation from both academic and industrial researchers paved the way for today’s successful HLS tools.

 

Mentor Booth

The booth features several videos covering Mentor’s news from DAC: three new technology announcements and a quick overview of the recent UltraSoC acquisition. There’s also a chat window where you can ask Mentor experts questions and there’s a feature that allows you to request meetings with Mentor representatives.

Because we can’t have coffee with you in person, for visiting Mentor’s booth you will receive a $5 Starbucks card (limited to one per person) via email shortly. Additionally, you will automatically be entered into our drawing for a Yeti 20oz Rambler/Tumbler simply by watching a video or engaging in a chat.*

 

*To qualify, you must be registered with a company email. Winners will be notified by email.  Please note the drawing excludes competitors and Mentor employees; the coffee cards are only available while supplies last; and the Yeti prizes can only be shipped to addresses within the USA. 

 

All of our designer track poster presentations will occur on Tuesday morning (July 21) apart from our designer track paper presentations on Tuesday, Monday & Wednesday (July 21 – 23). Attendees will also have the chance to enter to win some great prizes!

You can view the complete list of all our technical sessions and register here:

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