Siemens EDA Blogs

Siemens EDA’s mission is to help you engineer a smarter future faster. Read our latest blog posts to keep up to date on the latest tools, trends, methodologies and offerings in IC, advanced packaging and PCB systems electronics design, verification and manufacturing.

How IROC Technologies leveraged a new place-and-route tool to tape out an aerospace SoC in three months

In space, having precise, reliable equipment is essential and when experts can’t be precise, they need to know the possible...

Calibre IC Design & Manufacturing

DAC in December?? A Review of Calibre Design Solutions at DAC 2021

Did it feel a bit weird to be submitting research papers for DAC 2022 while packing to go to DAC...

By Calibre IC Design & Manufacturing

Calibre IC Design & Manufacturing

Is there a quick and easy way to calculate P2P resistance or current density between any two coordinates in my IC design layout?

February 28, 2022

By Li Li Why, yes, there is! As you know, Calibre® PERC™ logic-driven layout (LDL) current density (CD) and point-to-point...

By Calibre IC Design & Manufacturing

Electronic Systems Design

You Need to Control Your PCB Stackups!

February 23, 2022

Z-planner Enterprise contains all the tools you need to design and verify stackups on fast PCB designs. In addition to being able to calculate impedance and design valid stackups, you can run the field solver and perform cross-section analysis. And, it includes the industry’s largest dielectric materials library, including laminates. The result is a stackup design that will produce first-time-right results regardless of the fabricator.

Calibre IC Design & Manufacturing

The “next” technology node: ready or not, here it comes

February 22, 2022

By Shelly Stalnaker For years, decades even, the semiconductor industry has lived by the process node, which was originally named...

By Calibre IC Design & Manufacturing

Why some machine learning solutions succeed, and others fail

February 21, 2022

Note: Interested in getting to the right answer with your ML-enabled EDA solution? Head on to our on-demand webinar “Solido...

Calibre IC Design & Manufacturing

Physical design engineers…Learn the secret to generating signoff fill in P&R and accelerating your tapeouts

February 21, 2022

By Srinivas Velivala Place and route (P&R) engineers are always on the lookout for ways to optimize their design flows...

By Calibre IC Design & Manufacturing

Aim for power first for better PPA in place-and-route

February 21, 2022

Among the key metrics in IC place-and-route—performance, power, and area (PPA) — performance has traditionally been the primary focus. Low...

Tessent Solutions

Webinar: Smarter DFT architecture for advanced SoCs

February 18, 2022

Leonardo DaVinci said that “Simplicity is the ultimate sophistication.” Semiconductor design is a very complex process, and every step of...

By Tessent Solutions