This blog is a place to learn about electronic systems design, from PCB design to simulation and verification, to manufacturability and manufacturing execution.

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Why UHDI is pushing the limits of what’s possible 

In this episode of the Printed Circuit Podcast, host Steph Chavez sat down with Anaya Vardya, CEO of American Standard Circuits…

two engineers looking at a PCB design in Xpedition software

Elevating enterprise project success: The power of managed design review workflows in PCB design

A single error in a PCB layout can lead to costly re-spins, significant project delays, and even product failure in the field. Enter managed design review workflows for PCB design.

Cloud-native PCB design: a new era of agility, security, and scale 

In this episode of the Printed Circuit Podcast, guest host Matthew Walsh — stepping in while Steph Chavez attends PCB West — welcomes Adam…

PCB traces and impedance planning

Minimizing insertion loss: Why understanding trace width is critical at high frequencies

Material matters An engineer asked me recently about the relationship between trace width and insertion loss while adjusting dielectric height…

ECAD/MCAD collaboration is no longer optional — it’s survival 

In this episode of the Printed Circuit Podcast, host Steph Chavez welcomes two long-time friends and PCB design veterans —…

fabricator etching a PCB

Etch effects exposed: discover where your copper really goes

Etching inner layers involves cleaning the copper on both sides of the piece of laminate, applying a photoresist, exposing the photoresist to create the inner layer pattern, developing the resist, etching away the unwanted copper, and removing the etch resist. This process is automated in most shops and the chemistry is automatically monitored. As a result, the accuracy and repeatability is quite good. It is possible to etch inner layer traces using this process to an accuracy of ±0.5 mils. This accuracy control helps keep impedance within the tolerances required for transmission lines.

Graphic output of surface methodology from HyperLynx DSE

Accelerating the search through millions of “what if” scenarios

HyperLynx Design Space Exploration can help you optimize your design’s performance by exploring a very large design space in a fraction of the time required with traditional methods.

Design for Test

ASTER Technologies strengthens Siemens digital thread for optimized PCB manufacturability

Siemens EDA is pleased to announce its acquisition of ASTER Technologies, a trusted name within the PCB design industry with more than…

Design smarter, not harder: Evolving design reuse methodologies in EDA

In this episode of the Printed Circuit Podcast, host Steph Chavez explores the growing impact of design reuse in electronic design automation (EDA),…