Latest posts

Strapping in for Safety

White paper by Sumit Vishwakarma that explores the challenges, applications, benefits, and impact of analog fault simulation on chip design.

Masterclass – SPICE-accurate variation-aware verification best practices with Solido AI technologies

Note: If you’re interested in attending the Masterclass, register here and tune in February 20, 8am PT. In the ever-evolving…

Quantum semiconductor research forges ahead with steady breakthroughs

Quantum computing is an emerging technology Quantum computing promises a new generation of high-performance computers, with a completely novel approach…

The Resurgence of Japan’s Semiconductor Industry

The History of Semiconductors in Japan Japan has a rich history of innovation in the semiconductor industry. During the 1980s…

Exploring production-proven AI-powered EDA solutions with Solido Design Environment

Note: If you’re interested in knowing more about Solido Design Environment, check out this executive video by Amit Gupta, VP…

Bridging the gap between semiconductor IP providers and integrators

Note: To learn more about Solido Crosscheck’s QA exchange deck, check out the whitepaper https://resources.sw.siemens.com/en-US/white-paper-the-qa-exchange-deck-in-solido-crosscheck-enables-an-ip-qualification. This whitepaper discusses how the…

‘SPICE up’ your Verification this holiday season!

Just as I wrapped up my fancy Thanksgiving cooking marathon, I couldn’t help but draw parallels between the meticulous artistry…

IP QA best practices

A few months ago, it was reported that Apple was beginning the development of their A19 Bionic SoC using a…

Do you hear me now?

Siemens Symphony platform accelerates mixed-signal verification of DSP chips