Note: If you’re interested in attending the Masterclass, register here and tune in February 20, 8am PT.
In the ever-evolving landscape of technology, the recent release of Samsung’s Galaxy S24 smartphone series has set a new standard for AI innovations. Powered by Exynos 2400 processor, featuring cutting-edge Samsung 4nm process technology, this processor shows a step forward in performance and efficiency. However, behind what we see is a complex set of integrated circuits (ICs) that powers this magnificent performance and delivers the seamless user experience we’ve come to expect.
As we anticipate the impact of such advancements in the semiconductor applications, it becomes evident that achieving circuit design requirements is more challenging than ever. With every leap in the process technology, the need to manage variations efficiently and accurately becomes both increasingly challenging and crucial.
Join us for a Masterclass on SPICE-accurate variation-aware verification best practices!
On February 20th, we invite you to join me on this webinar where I will discuss the evolving challenges of variation-aware verification in IC design, uncover the most effective best practices, and explore how a methodology leveraging Solido Design Environment’s AI technologies can enhance SPICE-level variation-aware verification, accelerating verification runtime while enhancing coverage and accuracy.
Our masterclass, titled “Masterclass – SPICE-accurate variation-aware verification best practices with Solido AI-powered technologies,” equips you with the tools and strategies needed to manage SPICE-level variation analysis in your design faster, and with better accuracy.
Register now for the masterclass and mark your calendar for February 20th at 8am PT.