Next-generation RF, ESD and IO designs on display at TSMC 2023 OIP Ecosystem Forum

By Pradeep Thiagarajan

TSMC 2023 Open Innovation Platform® Ecosystem Forum is taking a world stage in North America, Europe, Taiwan, China, Israel and now Japan, spanning September through November in-person and virtual on-demand events. It is my pleasure to announce that TSMC has selected two unique topics, featuring Certus Semiconductor’s unique IPs with Siemens’ EDA verification technologies for presentation to the world-wide semiconductor community.

TSMC created the TSMC Open Innovation Platform® comprising of IP alliance, EDA alliance, Design center alliance, Cloud alliance, Value chain alliance and 3DFabric™ Alliance. The goal is to provide a robust and advanced design ecosystem, technologies and manufacturing excellence, supporting a comprehensive design technology infrastructure encompassing all IC implementation areas to reduce development barriers and help achieve first-time silicon success.

TSMC needs no introduction. They are a pioneer and a pure play foundry in creating process technologies that have been the foundation of semiconductor chip development and manufacturing world-wide. TSMC holds the gold medal in the global semiconductor foundry market share with almost 60% currently, now expanding with newer manufacturing plants around the globe to meet the growing market demands. Their process technologies span across planar, FinFET and now gate-all-around technologies supporting the full spectrum of  design applications, from 3um to 2nm. They further offer specialty process technologies for MEMS, CMOS Image Sensors, eFlash, mixed-Signal/RF, analog, HV and BCD applications. Their leadership is further solidified with TSMC 3DFabric, their family of 3D Silicon Stacking and Advanced packaging technologies.

Certus Semiconductor Inc. is a US based start-up specializing in unique RF, IO and ESD designs for both general purpose and custom applications. TSMC has been Certus’ foundational partner in providing reliable and scalable cutting-edge process technologies with ease of integration from mature processes to advanced nodes. This has enabled Certus to achieve highly complex, high performance, low power and low leakage designs to meet their customer requirements and applications. Certus has created niche high-voltage silicon-verified ESD and RF solutions in TSMC’s standard CMOS processes, which is extremely challenging for low-voltage processes. Certus has also built highly flexible IOs while targeting AEC grade reliability, sometimes radiation-hard grade reliability, with focus on supporting multi-protocols and voltages, while including power sequence independence, short protection and fail-safe mechanisms.

Siemens EDA is in partnership with Certus, enabling them for streamlined design and verification flows. Certus utilizes Siemens’ Analog FastSPICE (AFS) simulation platform for functional verification and Calibre platform for physical verification, to create robust RF, ESD and IO designs, validated with utmost precision and silicon correlation across TSMC process technologies. Furthermore, Siemens is a TSMC OIP Alliance partner in EDA, Cloud and 3DFabric, committed to enabling and supporting TSMC technologies and our mutual clients with products that do not compromise on quality.  Siemens’ Analog FastSPICE (AFS) is TSMC certified, and is qualified on all advanced nodes down to N2 with device and circuit qualifications. AFS supports TMI and TSMC reliability reference flows, including IC aging, real-time self-heating effects among other advanced reliability features.

At Siemens EDA, we constantly advance our technologies to address the evolving IC verification requirements from our customers. It has been our pleasure partnering with Certus to support their verification requirements for their ESD, RFIC and IO development. The following topics will be presented at TSMC 2023 OIP Ecosystem Forum by Stephen Fairbanks, CEO and CTO of Certus Semiconductor and me.

  1.  High Voltage RF and Analog Interfaces for Standard Low Voltage CMOS TSMC Processes
    • In-person presentation at TSMC OIP North America
    • Virtual presentation at the TSMC OIP Japan Virtual-on-Demand
  1. Multi-Protocol and Electrical IO flexibility catered for Automotive and Mobile Applications
    • In-person presentation at TSMC  OIP Japan event

Register below for the TSMC 2023 OIP Ecosystem Forum events:

  • North America in-person event on September 27th, 2023 at the Santa Clara Convention center
  • Japan in-person event on October 24th, 2023 at the Grand Hyatt Tokyo >> Stay tuned for TSMC link
  • Japan Virtual On-Demand event on November 16th, 2023. >> Stay tuned for TSMC link

Come embrace the innovation! We invite you to attend these presentations to learn how Certus Semiconductor is creating differentiated RF, ESD and IO design solutions with Siemens EDA’s verification technologies.

To learn more about Certus Semiconductor, visit:

To learn more about Siemens Custom IC Verification solutions, visit:

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