Library characterization takes too long – here’s how Solido Characterizer uses AI to change that

Tired of library characterization taking weeks? Solido Characterizer uses AI to slash runtime to days, boosting throughput by 7x with predictive, generative and agentic AI.

Introducing Custom IC Design Tool Tips: a new YouTube series for S-Edit and L-Edit users

The CICD team has launched Tool Tips! A YouTube series of short, practical walkthroughs for engineers working with S-Edit and L-Edit.

How NVIDIA is scaling Liberty verification for diverse IP using the Solido Characterization Suite

NVIDIA scales Liberty verification for diverse IP using Solido Characterization Suite, tackling challenges like diverse IP, consistency, and scalability for improved silicon quality.

Chiplet Summit 2026: Solido Simulation Suite tackles the verification complexities of 3D IC design

Solido Simulation Suite excels at Chiplet Summit 2026, tackling 3D IC verification complexities with SPICE-level accuracy for chiplet workflows.

Microchip’s journey to accelerated verification with Solido Additive Learning

Microchip leverages Solido Additive Learning’s AI-driven approach to accelerate iterative variation-aware verification by 3x to 20x, reducing re-verification cycles from weeks to hours.

Accelerating design innovation through scalable computing with cloud-ready Solido Simulation Suite on Amazon Web Services

Solido Simulation Suite on Amazon Web Services offers a cloud-ready solution to tackle the growing complexity of chip design by providing scalable, on-demand compute resources for efficient circuit simulation.

Solido and AI-powered EDA: TSMC certification, reference flow, and what it all means for advanced node design

Solido’s AI-powered EDA tools have earned TSMC certification and a place in the reference flow for A14. Here’s what that means for designers working at advanced process nodes.

Multi-die verification and the chiplet simulation challenge

Multi-die verification: the chiplet simulation challenge

When multiple dies, potentially from different vendors and different process nodes, come together in a single package, traditional simulation approaches fall short.

How NXP Achieved Robust Verification and Portfolio Re-characterization of Liberty IP with Solido Characterization Suite

At the Design Automation Conference (DAC), Siemens EDA and NXP collaborated to showcase innovative methodologies that directly address two of the most critical challenges in library characterization: accelerating Liberty (.lib) characterization and verification. Together, we presented solutions that redefine traditional approaches, creating efficient and reliable workflows that advance NXP’s design process.