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How agentic AI is shaping the future of custom IC design and verification: Solido at DAC 2026

The Solido Custom IC (CIC) team is heading to DAC 2026 with a full program of technical sessions, panel discussions and poster presentations covering the latest developments in AI-powered custom IC design and verification, including our newest agentic AI capabilities. Join us from July 27–29 in Long Beach, CA to see how Solido AI solutions are being applied to real-world design challenges.

Here’s a full overview of our activities at DAC, including when and where you can connect with our team.

Interactive AI experience

Visitors to the Siemens EDA booth — #1327 on the exhibit floor — can explore our interactive AI experience, where 12 Solido AI demos will be showcased. Highlights include our latest agentic AI demos across the custom IC workflow and a glimpse into how our AI agents are pushing the boundaries of autonomous custom IC design. This is your opportunity to see our AI solutions in action and speak directly with the engineers and experts behind them. Stop by any time during DAC.

DAC day 1: July 27

Panels and presentations with Amit Gupta

Amit Gupta, Chief AI Strategy Officer and Senior Vice President and General Manager, Solido CIC and Siemens EDA AI, is featured across two sessions at this year’s DAC. Catch his TechTalk with NVIDIA, followed by his appearance on Cooley’s DAC Troublemaker Panel.

11:15am – 12:00pm
Location: DAC Pavilion, Exhibit Floor


TechTalk – From Tools to Agents: Realizing Fully Autonomous EDA Workflows
3:00pm – 3:45pm
Location: DAC Pavillion, Exhibit Floor


Cooley’s DAC Troublemaker Panel

Engineering track presentations

1:45pm – 2:00pm
Location: Seaside Ballroom B 
Novel Methodology: Adaptive AI and Additive AI for High-Sigma Standard Cell Library Verification (Samsung)
2:30pm – 2:45pm
Location: Seaside Ballroom B 
A Unified QA/QC Framework for Intel Foundry Library Validation using Siemens Solido Crosscheck IP Validation Suite (Intel)

Engineering track posters

5:00pm – 6:00pm
Location: Poster Reception – Exhibit Floor
A Unified QA/QC Framework for Intel Foundry Library Validation using Siemens Solido Crosscheck IP Validation Suite (Intel)
5:00pm – 6:00pm
Location: Poster Reception – Exhibit Floor
Liberty Based Profiling for IP Benchmarking (NXP)
5:00pm – 6:00pm
Location: Poster Reception – Exhibit Floor
Novel Methodology: Adaptive AI and Additive AI for High-Sigma Standard Cell Library Verification (Samsung)

DAC day 2: July 28

Siemens-hosted session

Solido agentic AI: Transforming every step of the custom IC design and verification workflow
12:00pm – 1:30pm┃Lunch provided
Location: Long Beach Convention Center

Speakers:

  • Chengcheng Liu (NVIDIA)
  • Mandar Deshpande (Microchip)
  • Pushkar Dixit (Tektronix)
  • Sathishkumar Balasubramanian (Siemens EDA)

Join us for a lunch and learn session where we’ll showcase how Solido’s agentic AI and broader Solido AI technologies, spanning machine learning to purpose-built agents, are transforming every stage of the custom IC design and verification workflow.

A live Q&A will give attendees the opportunity to explore real-world use cases and customer success examples, adoption strategies and the future direction of AI in custom IC design. Learn more and register here.

Pavilion panel discussions

Build vs Buy: Who Owns the Intelligence Behind Tomorrow’s Chips?
3:00pm – 3:45pm
Location: DAC Pavilion, Exhibit Floor

AI is transforming chip design, but who truly owns the intelligence when proprietary data and evolving models are involved? This panel explores the build-versus-buy dilemma for AI in semiconductor design, focusing on trust, data ownership and accountability. Amit Gupta joins participants from Alphacore, Analog Bits, Arteris, and IImda for this discussion moderated by Daniel Nenni from SemiWiki.

Is EDA AI Delivering on Its ROI Promise?
4:00pm – 4:45pm
Location: DAC Pavilion, Exhibit Floor

AI in EDA is moving fast, but engineering teams want results, not promises. Join Jeff Dyck, Vice President of R&D, Solido Custom IC and Siemens EDA AI, for a panel session with Microsoft, ARM, Broadcom and NVIDIA that cuts through the hype and asks the question that matters right now: Is EDA AI delivering on its ROI promise?

Engineering track posters

5:00pm – 6:00pm
Location: Poster Reception – Exhibit Floor
An Optimized Full-Chip Analog Mixed-Signal (AMS) Verification Approach for PVT Calibration in FPGA Systems (Microchip)
5:00pm – 6:00pm
Location: Poster Reception – Exhibit Floor
A Novel Design Approach for Optimized EMC and Thermal Performance in Next-Generation Automotive Applications (Denso)
5:00pm – 6:00pm
Location: Poster Reception – Exhibit Floor
Enhancing the Robustness of Impinj RFID through the Application of AI-powered Design Flow (Impinj)
5:00pm – 6:00pm
Location: Poster Reception – Exhibit Floor
Identifying Weakest Links: A Cell Scoring Metric for Robust Design in Advanced Nodes (NXP)
5:00pm – 6:00pm
Location: Poster Reception – Exhibit Floor
Library PPA DTCO with Library Profiler (Samsung)
5:00pm – 6:00pm
Location: Poster Reception – Exhibit Floor
Meeting EDA workload capacity needs with AWS for Siemens’ Solido Custom IC technologies (AWS)

DAC day 3: July 29

Engineering track presentation

11:30am – 11:45am
Location: Seaside Ballroom B 
Screening Analog Anomality for Security Vulnerability in Digitally Verified Crypto Cores (Kobe University/Secafy)

Engineering track posters

3:00pm – 4:00pm
Location: Poster Reception – Exhibit Floor
Accelerating Memory Cache Verification with AI-Powered Batch Flow Methodology (Qualcomm)
3:00pm – 4:00pm
Location: Poster Reception – Exhibit Floor
Accurate Characterization Methodology for Combo-IO design with Concurrent Switching Outputs for Precise Power Analysis at SoC (ST)
3:00pm – 4:00pm
Location: Poster Reception – Exhibit Floor
Achieving “Zero Defect” Quality in Automotive Ethernet Solutions with AI-Accelerated Trimming & Verification (NXP)
3:00pm – 4:00pm
Location: Poster Reception – Exhibit Floor
AI-accelerated optimization Flow for Robust Analog and Mixed-Signal Circuit Design Against Process Variation (EKE Power)
3:00pm – 4:00pm
Location: Poster Reception – Exhibit Floor
AI-Accelerated Signoff Verification and Glitch Analysis for Single and Multibit Level Shifters (Intel)
3:00pm – 4:00pm
Location: Poster Reception – Exhibit Floor
Boosting IP Quality and Productivity through IPdelta Profile-Driven Change Detection (ST)
3:00pm – 4:00pm
Location: Poster Reception – Exhibit Floor
Bridging Analog Fidelity and Digital Performance in Chiplet Interface Mixed-Signal IP Verification (Analog Port)
3:00pm – 4:00pm
Location: Poster Reception – Exhibit Floor
Comprehensive SoC Power System Verification Using Optimized Mixed-Signal Verification Methodology (Microchip)
3:00pm – 4:00pm
Location: Poster Reception – Exhibit Floor
Screening Analog Anomality for Security Vulnerability in Digitally Verified Crypto Cores (Kobe University/Secafy)

Connect with us at DAC 2026 and visit the Siemens EDA booth to speak with our team of experts. Explore the latest advancements in Solido AI, see our agentic AI demos in action and discuss how our AI solutions can address your specific design challenges. We look forward to seeing you there!

Mamoona Ahmad

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This article first appeared on the Siemens Digital Industries Software blog at https://blogs.sw.siemens.com/cicv/2026/07/10/agentic-ai-solido-at-dac-2026/