Chiplet Summit 2026: Solido Simulation Suite tackles the verification complexities of 3D IC design
In 2011, TSMC introduced Chip-on-Wafer-on-Substrate (CoWoS) technology, representing their first generation of advanced packaging. Since then, the semiconductor industry has shifted its focus from exclusively following Moore’s Law to pursuing increased vertical chip density. The integration of heterogeneous chips presents distinctive challenges, prompting the semiconductor industry to establish a specialized forum, which culminated in the launch of the Chiplet Summit.
Chiplet Summit held its first conference in 2023 in San Jose. With the rapid advancement in 2.5D and 3D chip design, Chiplet Summit has quickly become a focal point for discussions on chiplet architecture within the industry. The event addresses challenges related to heterogeneous integration, 3D stacking, and advanced packaging testing, while placing particular emphasis on industry standards such as die-to-die connectivity with UCIe.
It was against this backdrop that Siemens Solido Custom IC platform made its mark at the 4th Chiplet Summit. Solido SPICE, part of Solido Simulation Suite, represents a major step forward in chiplet design verification, bringing SPICE-level accuracy to system-level chiplet workflows. As outlined in our whitepaper, “Combining SPICE with IBIS-AMI: Solving advanced signal integrity verification challenges with Solido SPICE“, the technology supports chiplet design through its integration with IBIS-AMI models. This allows for accurate representation of SPICE non-linear effects alongside abstracted model behaviors, enabling a precise analysis of eye diagrams at the chiplet output. Notably, Solido SPICE with IBIS-AMI support was selected for a technical presentation at the 4th Chiplet Summit held in February 2026 in Santa Clara, titled Enabling Advanced Transceiver Verification for Chiplet Architectures.
In this presentation, Scott Wedge, R&D Director at Siemens EDA, discussed the challenges associated with die-to-die transceiver verification and highlighted the advantages of IBIS-AMI model processing by Solido SPICE, for enhanced system-level verification in chiplet design. In addition to IBIS-AMI support, the Siemens EDA Custom IC team presented several features tailored for chiplet development, including multi-technology support (MTS) and mixed-signal capabilities enabled by Symphony. The ongoing advancements in the Solido Simulation Suite demonstrate our continued commitment to addressing the evolving needs of chiplet design. We are dedicated to developing innovative solutions and supporting chiplet designers as they navigate the era beyond traditional Moore’s Law scaling.
Ready to future-proof your chiplet design flow? Explore how the Solido Simulation Suite can help
