Solido and AI-powered EDA: TSMC certification, reference flow, and what it all means for advanced node design
The discussion around EDA technologies has always centered on a powerful combination: what the tool can do and what the designer can build with it. That combination has never been more compelling than it is now, in the era of AI-powered EDA. This week, Siemens announced the latest developments in its collaboration with TSMC to advance AI for semiconductor design. The collaboration touches tools across the full EDA workflow: from physical verification with Calibre, to digital implementation with Aprisa, to custom IC design and verification with Solido, to the Fuse EDA AI system, which brings multi-step, multi-tool agentic automation to complex semiconductor workflows.
AI delivers its full value when designers can build with what it produces with complete confidence. In the semiconductor industry, that confidence has a name. It is called certification. Among the software tools covered in that collaboration, this piece takes a closer look at Solido Custom IC technologies, and the role that certification plays for designers working at TSMC’s most advanced process nodes.
The stakes at advanced process nodes
At nodes like A14, A16, and N2P, the physical behavior of devices is extraordinarily sensitive. Variation across process, voltage, and temperature, effects that might be manageable at older nodes, can determine whether a design works or fails at the leading edge. Add in aging effects, self-heating, and the complexity of analog, mixed-signal, and memory designs, and the simulation problem demands both speed and rigorous physical accuracy. A tape-out at an advanced node can cost tens of millions of dollars, and the margin for error shrinks with every new process generation. In this environment, what separates good tools from great ones is the ability to deliver speed and accuracy together.
Certification is how AI-powered tools earn their place in the design flow
When TSMC certifies a tool for a specific process node, it is making a specific and consequential claim: the outputs of this tool are physically accurate enough to base real design decisions on. It is not certifying a feature set or a benchmark result. It is certifying that what the tool computes matches the behavior of real silicon at that node, under the conditions that matter to designers working at the leading edge.
Solido Simulation Suite is now certified for SPICE accuracy across TSMC’s N3A, N2P, A16, and A14 process technologies. Designers working on analog, mixed-signal, RF, standard cell, and memory designs at those nodes can use Solido’s AI-powered simulation outputs as the basis for real decisions, confident that those outputs have been validated against TSMC’s own physical models and meet the accuracy bar that advanced node design demands.
Inside the reference flow: another level of validation
TSMC certification carries weight, but inclusion in the reference flow is a deeper validation. TSMC’s Custom Design Reference Flow (CDRF) for A14 incorporates Solido at two distinct levels, each reflecting a different dimension of what advanced node design requires. Reliability-aware simulation, accounting for IC aging, real-time self-heating, and Safe Operating Area (SOA) checks, is embedded in the flow because those are not theoretical effects at A14. They are real design challenges that surface before tape-out and must be addressed with tools that can be trusted to get them right. Solido Design Environment for advanced variation-aware verification is also incorporated, helping designers navigate the extraordinary sensitivity that A14 demands across every stage of the design process.
The collaboration between Solido technologies and TSMC further extends into the realm of silicon photonics. Solido tools, including Solido Simulation Suite and L-Edit software, are part of Siemens’ 3D IC flow that support design and verification of TSMC Compact Universal Photonic Engine (TSMC COUPE™) technology as that collaboration continues to develop.
For designers, the implications are direct. When a tool is part of the reference flow, it is there as a trusted component. Every stage of the project looks different as a result. Simulation results carry the weight of TSMC’s own validation. Reliability checks are not an afterthought added late in the cycle but a structured part of the process from the start. And when a design reaches tape-out, the confidence behind it is not based on assumption; it is based on a verified, certified workflow that has been tested against the physical realities of the process node.
What this means for designers working at the leading edge of process nodes
The question of what a tool can do and what a designer can build with it is not a philosophical one at advanced nodes. It is an engineering opportunity. Certification is how that opportunity gets realized. And earning a place in TSMC’s reference flow for A14 is how Solido has demonstrated that it delivers. In the era of AI-powered EDA, the tools that matter are the ones that give designers the confidence to move faster and push further. That confidence is not assumed. It is earned, certified, and built into the design flow.
