Maximizing the capabilities of Siemens’ L-Edit for Custom IC Layout

Solido Custom IC Design team shares L-Edit tips: Flylines, Highlight Connected and Calibre Real Time for efficient layout.

How STMicroelectronics achieved faster standard cell library verification with AI-powered Solido Library Verifier solution

STMicroelectronics achieved a 12X speedup in standard cell library verification using AI-powered Solido Library Verifier, here’s how they did it.

Library characterization takes too long – here’s how Solido Characterizer uses AI to change that

Discover how Solido Characterizer uses AI to deliver 7x faster library characterization — turning weeks of runtime into days without sacrificing accuracy.

Introducing Custom IC Design Tool Tips: a new YouTube series for S-Edit and L-Edit users

The CICD team has launched Tool Tips! A YouTube series of short, practical walkthroughs for engineers working with S-Edit and L-Edit.

How NVIDIA is scaling Liberty verification for diverse IP using the Solido Characterization Suite

NVIDIA scales Liberty verification for diverse IP using Solido Characterization Suite, tackling challenges like diverse IP, consistency, and scalability for improved silicon quality.

Chiplet Summit 2026: Solido Simulation Suite tackles the verification complexities of 3D IC design

Solido Simulation Suite excels at Chiplet Summit 2026, tackling 3D IC verification complexities with SPICE-level accuracy for chiplet workflows.

Microchip’s journey to accelerated verification with Solido Additive Learning

Microchip leverages Solido Additive Learning’s AI-driven approach to accelerate iterative variation-aware verification by 3x to 20x, reducing re-verification cycles from weeks to hours.

Accelerating design innovation through scalable computing with cloud-ready Solido Simulation Suite on Amazon Web Services

Solido Simulation Suite on Amazon Web Services offers a cloud-ready solution to tackle the growing complexity of chip design by providing scalable, on-demand compute resources for efficient circuit simulation.

Multi-die verification and the chiplet simulation challenge

Multi-die verification: the chiplet simulation challenge

When multiple dies, potentially from different vendors and different process nodes, come together in a single package, traditional simulation approaches fall short.