Latest posts

Optimizing design implementation with Calibre LEF/DEF technology

By James Paris and Armen Asatryan Ever hear the saying “When all you have is a hammer, everything looks like…

Curves ahead for IC manufacturing

By John Sturtevant It turns out that the ideal mask pattern to print such a circle is in fact a…

Building the bridge between GDS and OASIS

By Shelly Stalnaker Switching from GDS to OASIS format can bring a host of benefits, but only if you make…

Does your parasitic extraction work in 5G IC designs?

By Salma Ahmed and Karen Chow The next-generation 5G mobile communication network is a heterogeneous network providing significant performance advantages…

A touchy subject: RF IC layout verification

By Neel Natekar Radio frequency (RF) circuitry is an essential component of many of the critical applications we now rely…

The mPower toolsuite wins Elektronik Product of the Year for Software Tools!!

By Shelly Stalnaker Every year, the editors of Elektronik in Germany compile a list of the most interesting and innovative…

Smoothing the path to manufacturing success begins with CMP simulation and fill optimization

By Ruben Ghulghazaryan, Davit Piliposyan, Zhengfang Liu, Chunshan Du, Jeff Wilson, Qijian Wan, Xinyi Hu, Zhixi Chen Chemical-mechanical polishing (CMP)…

How to get to Win-Win-Win in conflict management

By Shelly Stalnaker & Calibre Design staff Anyone who’s been through conflict management training understands the three basic scenarios. There’s…

Innovations in physical verification tools and technologies keep the IC industry moving forward

By John Ferguson A few years ago, I was invited to present a paper discussing the advances in physical verification…