Design with Calibre

The industry-leading Calibre toolsuite provides physical verification (DRC), circuit verification (LVS, PEX), and reliability verification (PERC), as well as Calibre DFM optimization, to ensure IC designs will deliver the power, performance, and foundry yield today’s markets demand. Across all process nodes and design styles, innovative functionality ensures the Calibre toolsuite provides accurate, efficient, comprehensive IC verification while minimizing resources and tapeout schedules.

Latest posts

Migrating Consumer Electronics to the Automotive Market with Calibre PERC

April 28, 2015

By Matthew Hogan, Mentor Graphics Calibre PERC can help you succeed in the automotive market

By Design With Calibre

6 MIN READ

Cutting Fab Costs and Turnaround Time with Smart, Automated Resource Management

April 21, 2015

By Mark Simmons, Mentor Graphics Simple in theory, challenging in reality

By Design With Calibre

4 MIN READ

Free Is a Good Price, Especially for Process Design Kits

April 14, 2015

By Joseph Davis, Mentor Graphics The freePDK15 and its associated 15 nm Open Cell Library are now available!

By Design With Calibre

4 MIN READ

Accurate Lithography Simulation for Silicon Photonics

April 7, 2015

By Joe Kwan, Mentor Graphics Precise curved geometries are vital to making silicon photonics technology work

By Design With Calibre

5 MIN READ

Designing and Testing FinFet-based IC Designs

March 31, 2015

By Carey Robertson and Steve Pateras, Mentor Graphics Are your processes ready for finFETs?

By Design With Calibre

4 MIN READ

Self-Aligned Double Patterning, Part Deux

March 24, 2015

By David Abercrombie, Mentor Graphics Part 2 of a walk-through of the SADP process.

By Design With Calibre

6 MIN READ

Auto IC Market: Revving Up Product Line Means Revving Up Reliability

March 17, 2015

By Matthew Hogan, Mentor Graphics Designing electronics for automotive use means meeting stringent safety and reliability standards.

By Design With Calibre

4 MIN READ

Sign-off lithography simulation and multi-patterning must play well together

March 10, 2015

By Joe Kwan, Mentor Graphics At 20 nm and below, designers must ensure their lithography simulation can incorporate and analyze…

By Design With Calibre

4 MIN READ

2-5X Productivity Improvement in 14FDSOI Layout Design: STMicroelectronics Experience with Calibre RealTime

March 2, 2015

By Atul Bhargava and Mehak Malhotra, STMicroelectronics, India and Srinivas Velivala, Mentor Graphics Rather than just fixing DRC errors as…

By Design With Calibre

6 MIN READ