Design with Calibre

The industry-leading Calibre toolsuite provides physical verification (DRC), circuit verification (LVS, PEX), and reliability verification (PERC), as well as Calibre DFM optimization, to ensure IC designs will deliver the power, performance, and foundry yield today’s markets demand. Across all process nodes and design styles, innovative functionality ensures the Calibre toolsuite provides accurate, efficient, comprehensive IC verification while minimizing resources and tapeout schedules.

Latest posts

Reported Death of Moore’s Law Premature?

November 10, 2015

By Michael White, Mentor Graphics Is Moore’s Law dying? A look at the latest process node activity and technology

By Design With Calibre

5 MIN READ

Together At Last – Combining Netlist and Layout Data for Power-Aware Verification

November 3, 2015

By Beth Martin, with Sridhar Srinivasan, Yi-Ting Lee, and Frank Feng, Mentor Graphics Reliability checks on multiple-power-domain and mixed-signal designs…

By Design With Calibre

4 MIN READ

MEMS Technology and Manufacturing on the Microscale

October 27, 2015

By Carey Robertson and Khaled AbouZeid, Mentor Graphics Designers incorporating MEMS devices into high-volume CMOS ICs need new processes, data,…

By Design With Calibre

6 MIN READ

Deja Vu for CMP Modeling?

October 20, 2015

By Jeff Wilson, Mentor Graphics With manufacturing innovations and new DFM solutions, CMP modeling is gaining renewed popularity

By Design With Calibre

5 MIN READ

Assembly Design Kits are the Future of Package Design Verification

October 14, 2015

By John Ferguson, Mentor Graphics Like PDKs for ICs, qualified assembly design kits for packages can ensure the quality and…

By Design With Calibre

6 MIN READ

Parasitic extraction for touchscreen designs

October 6, 2015

By Mohamed ElRefaee, Mentor Graphics Accurate parasitic extraction of touchscreens is essential for ensuring the high-quality performance the market demands

By Design With Calibre

5 MIN READ

Electrical Overstress Detection and Debugging

September 29, 2015

By Dina Medhat, Mentor Graphics Automated voltage propagation provides an accurate way to detect and correct those hard-to-find EOS conditions…

By Design With Calibre

5 MIN READ

Case Studies in P&R Double Patterning Debug: Part Two

September 22, 2015

David Abercrombie continues his expert advice to P&R and chip finishing engineers on understanding and debugging multi-patterning errors accurately and…

By Design With Calibre

8 MIN READ

Case Studies in Double-Patterning Debug: Part One

September 15, 2015

By David Abercrombie, Mentor Graphics Multi-patterning errors in P&R layouts can be intricate, and their solutions may not be obvious

By Design With Calibre

10 MIN READ