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P&R Designers— How to quickly analyze and debug signoff DRC errors in P&R, using the Calibre RVE interface

P&R Designers— How to quickly analyze and debug signoff DRC errors in P&R, using the Calibre RVE interface

Want to quickly analyze and debug signoff DRC errors in P&R? The Calibre RVE multi-viewer function lets you sync multiple…

IC designers: find your focus and priorities during DRC debug

IC designers: find your focus and priorities during DRC debug

By Srinivas Velivala – Mentor, A Siemens Business Layout design verification gets exponentially harder with each new process technology node….

Highlights from SPIE – Successes and advancements over the past year

Highlights from SPIE – Successes and advancements over the past year

By Gandharv Bhatara – Mentor, A Siemens Business At the 43rd SPIE Advanced Lithography conference in San Jose that ran from…

Calibre PERC electrical reliability verification – why you need it at every node

Calibre PERC electrical reliability verification – why you need it at every node

By Juan C. Rey, Vice President of Engineering, Calibre – Mentor, A Siemens Business If you’re not performing electrical reliability…

Watch & Learn: Reducing Time-to-Support

Watch & Learn: Reducing Time-to-Support

By Srinivas Velivala – Mentor, A Siemens Business If you’re a chip designer or a CAD person trying to figure…

Simplify and speed up early floorplan verification with incremental interface DRC

Simplify and speed up early floorplan verification with incremental interface DRC

By James Paris – Mentor, A Siemens Business In early floorplan verification, incomplete blocks produce numerous interface errors. Incremental interface…

Establishing a reliability baseline provides confidence and consistency

Establishing a reliability baseline provides confidence and consistency

By Matthew Hogan – Mentor, A Siemens Business Design companies must establish baseline robustness and reliability criteria throughout the entire…

Get to yield ramp faster…even with new design styles

Get to yield ramp faster…even with new design styles

By Wael Manhawy and Joe Kwan – Mentor, A Siemens Business Having trouble ramping yield for new, unproven design styles? Experiments…

HDAP connectivity verification—what’s your solution?

HDAP connectivity verification—what’s your solution?

By Tarek Ramadan – Mentor, A Siemens Business New HDAP designs like FO-WLP require package-level connectivity verification tools and processes….