Latest Posts

Sign-off lithography simulation and multi-patterning must play well together

By Joe Kwan, Mentor Graphics At 20 nm and below, designers must ensure their lithography…

2-5X Productivity Improvement in 14FDSOI Layout Design: STMicroelectronics Experience with Calibre RealTime

By Atul Bhargava and Mehak Malhotra, STMicroelectronics, India and Srinivas Velivala, Mentor Graphics Rather than…

The Route to Faster Physical Verification and Better Designs

By Nancy Nguyen and Jean-Marie Brunet, Mentor Graphics Using the most accurate and up-to-date signoff…

What about MEMS?

By Carey Robertson, Mentor Graphics With circuit performance driven by capacitance values, accurate calculations are…

A Look Behind the Mask of Multi-Patterning

By Michael White, Mentor Graphics An overview to the mystery of Multi-Patterning…

My Design’s Interconnect Has Enough Wire Width to Withstand ESD… Doesn’t It?

By Frank Feng, Mentor Graphics Electrostatic discharge can destroy a circuit, but designing adequate protection…

Self-Aligned Double Patterning, Part One

By David Abercrombie, Mentor Graphics A walk-through of the SADP process for success.    …

Are multi-patterning corners for parasitic extraction really necessary for 16/14 nm?

By Karen Chow, Mentor Graphics How does multi-patterning impact parasitic extraction? How many corners do…

How to Survive the Perfect Storm of Changing Fill Requirements

By Jeff Wilson, Mentor Graphics Using hierarchy in the fill process provides greater control for…