By Neel Natekar – Mentor, A Siemens Business
AI/ML chips are seeing growing adoption, but ensuring reliable operation and trusted performance is key to their success. Do you have the knowledge and tools you need?
Artificial intelligence (AI) and machine learning (ML) are becoming ubiquitous across a wide range of applications covering nearly every aspect of our daily lives, from advanced driver assistance systems (ADAS) used inside vehicles, to medical diagnostics and care delivery, to prediction and real-time management of the demand curve for electricity. Just those few examples demonstrate the criticality of ensuring reliability in these chips, both in the performance they deliver and their expected product life.
The problem is that AI and ML chip design and verification doesn’t fit neatly into a one-size-fits-all solution. Companies employ a wide range of design options, from graphic processing units (GPUs) to field-programmable gate arrays (FPGAs) to application-specific integrated circuits (ASICs). They may even combine different compute core types to handle different types of processing tasks. This variability, combined with the size and complexity of these designs, creates the need for a whole new level of reliability verification.
Traditionally, designers used their experience and expertise in combination with multiple verification techniques (including both manual inspection and circuit simulation) to determine reliability. Inevitable human error, insufficient coverage, lack of scalability, and excessively long runtimes mean that approach simply doesn’t work on these huge designs, with transistor counts on the order of millions, and sometimes even multi-billions. A solution that provides both automated and foundry-qualified reliability verification is essential to the continued growth and adoption of trusted AI/ ML technology.
The Calibre™ PERC™ reliability platform leverages a rich set of features and functionality to deliver fast, foundry-qualified reliability verification. Its innovative processing combines both netlist and layout information from a design to precisely evaluate a wide range of potential reliability issues. It also uses the Calibre platform’s multi-threaded (MT) and multi-threaded flexible (MTFlex) scaling, which distributes tasks to multiple CPUs and/or remote machines to provide fast, efficient execution of verification processes on large and complex chips like AI/ML designs. Best of all, the Calibre PERC reliability platform is foundry-qualified, so you can depend on the results for accurate and comprehensive reliability verification.
From transistor-level reliability verification to operational safety and lifetime performance, the Calibre PERC reliability platform helps AI/ML designers analyze and manage all reliability aspects of their AI/ML designs, including target environment, operating conditions, and foundry reliability criteria. Identifying and fixing reliability violations before tape-out not only minimizes the chance of costly circuit malfunctions or failures, but also helps support and expand the use of AI/ML technology.
To get the full details, download a copy of our white paper, Reliability verification for AI and ML processors.