Electronics & Semiconductors - Semiconductor Packaging

Siemens 3D IC heterogeneous semiconductor packaging workflows catapult design teams into the future of IC design today.

Workflows for tackling heterogeneous integration of chiplets for 2.5D/3D semiconductor packaging

January 11, 2024

Workflows for tackling heterogeneous integration of chiplets for 2.5D/3D semiconductor packaging.

By John McMillan

4 MIN READ

Parasitic extraction technologies: Advanced node and 3D-IC design

January 2, 2024

Advanced nodes and 3D-IC packages require new and enhanced parasitic extraction processes that can resolve a variety of complex parasitic issues in these designs.

By John McMillan

3 MIN READ

Impacts of 3D IC on the future

December 20, 2023

3D IC technology development started many years ago well before the slowing down of Moore’s law benefits became a topic…

By John McMillan

3 MIN READ

System-level, post-layout electrical analysis for high-density advanced packaging (HDAP)

December 18, 2023

HDAP designs like FOWLP need post-layout simulation (analog) and post-layout STA (digital) flows to augment basic physical verification DRC and LVS.

By John McMillan

3 MIN READ

Crossing the chasm: Bringing SoC and package verification together

December 8, 2023

3D IC package designers need assembly-level LVS for HDAP verification.

By John McMillan

2 MIN READ

Package designers need assembly-level LVS for HDAP verification

December 5, 2023

While advanced integrated circuit (IC) packaging is a fast-growing market, comprehensive package verification still has a ways to go. Unique…

By John McMillan

2 MIN READ

Understanding 3D IC Technology: Unveiling the Future of Integrated Circuits

November 6, 2023

Delve into the world of 3D IC technology, its architecture, benefits, and applications. Learn how it’s reshaping the future of integrated circuits for enhanced performance and efficiency.

By John McMillan

6 MIN READ