By John Ferguson, Mentor Graphics FO-WLP combines multiple die from heterogeneous processes into a compact package, and that’s a good…
By Matthew Hogan, Mentor Graphics Fast simulation and PEX are both crucial to interconnect robustness verification. Can your tools scale…
By Michael White, Mentor Graphics Automated pattern matching can solve a wide range of design verification issues. Are you in…
By Yousry Elmaghraby, Mentor Graphics Choosing the best PEX method for your full-chip or SoC design is essential. But how…
By David Abercrombie and Alex Pearson, Mentor Graphics Applying ECOs to multipatterned designs can be a nightmare, unless you plan…
By Matthew Hogan, Mentor Graphics The increasing use of SoC designs turns efficient IC design and validation into a team…
By Valeriy Sukharev, Jun-Ho Choy, Armen Kteyan and Henrik Hovsepyan, Mentor Graphics Optimizing power usage for mobile devices at advanced…
By Karen Chow, Mentor Graphics Signal integrity analysis at advanced nodes requires new and enhanced parasitic extraction techniques
By Michael White, Mentor Graphics Will fan-out wafer-level packaging be the impetus that pushes 3D-IC into mainstream acceptance?
