LEF/DEF IO Ring Check Automation

LEF/DEF IO Ring Check Automation

By Matthew Hogan, Mentor Graphics Designing today’s complex system-on-chips (SoCs) requires careful consideration when planning input/output (IO) pad rings…  

Correct by Construction and Other Myths

Correct by Construction and Other Myths

By Joseph Davis, Mentor Graphics Is “correct by construction” a myth?

Why Do We Need Assembly Design Kits for Packages?

Why Do We Need Assembly Design Kits for Packages?

By John Ferguson and Tarek Ramadan, Mentor Graphics Why do we need assembly design kits for IC packages?

Reported Death of Moore’s Law Premature?

Reported Death of Moore’s Law Premature?

By Michael White, Mentor Graphics Is Moore’s Law dying? A look at the latest process node activity and technology

Together At Last – Combining Netlist and Layout Data for Power-Aware Verification

Together At Last – Combining Netlist and Layout Data for Power-Aware Verification

By Beth Martin, with Sridhar Srinivasan, Yi-Ting Lee, and Frank Feng, Mentor Graphics Reliability checks on multiple-power-domain and mixed-signal designs…

MEMS Technology and Manufacturing on the Microscale

MEMS Technology and Manufacturing on the Microscale

By Carey Robertson and Khaled AbouZeid, Mentor Graphics Designers incorporating MEMS devices into high-volume CMOS ICs need new processes, data,…

Deja Vu for CMP Modeling?

Deja Vu for CMP Modeling?

By Jeff Wilson, Mentor Graphics With manufacturing innovations and new DFM solutions, CMP modeling is gaining renewed popularity

Parasitic extraction for touchscreen designs

Parasitic extraction for touchscreen designs

By Mohamed ElRefaee, Mentor Graphics Accurate parasitic extraction of touchscreens is essential for ensuring the high-quality performance the market demands

Electrical Overstress Detection and Debugging

Electrical Overstress Detection and Debugging

By Dina Medhat, Mentor Graphics Automated voltage propagation provides an accurate way to detect and correct those hard-to-find EOS conditions…