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How can I run reliability checks early in the design cycle?

By Hossam Sarhan and Alexandre Arriordaz With the increasing complexity of design layouts and shorter tapeout cycles, waiting until signoff…

Siemens EDA celebrates 20 years of collaboration with imec

By Germain Fenger, Director of Product Management RET modelingCalibre Semiconductor Manufacturing solutions This year marks the 20th anniversary of the…

First out of the (3DIC) box: How Siemens EDA is using the TSMC 3Dblox standard to change 3DIC verification

By John Ferguson In recognition of the growing need for a more holistic approach to three-dimensional integrated circuit (3DIC) design,…

A novel methodology for EM assessment in on-power grids can improve power, time-to-market, and design cost

By Valeriy Sukharev, Armen Kteyan, Jun-Ho Choy Achieving an accurate assessment of electromigration (EM)-induced failure is essential to developing a…

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The secret superpower of early design verification

By Kesmat Shahin How many times, as you traversed across design stages and ran countless iterations, have you wished that…

Help! I’m not an ESD expert! Reducing ESD verification complexity

By Abdellah Bakhali If you’re not an electrostatic discharge (ESD) expert (and let’s face it, most of us aren’t), verifying…

Automated common resistance checking…it’s the smart thing to do!

By Hossam Sarhan Work smarter, not harder. Isn’t that what everyone is always telling you? Of course, it’s excellent advice,…

A software migration that improves productivity? The Calibre Interactive tool has a (new) GUI for that…

By Slava Zhuchenya Software migration can be a dreaded endeavor, especially for electronic design automation (EDA) tools that design companies…

Find high resistance faster in P2P violations with interactive P2P analysis

By Slava Zhuchenya So your net trace has too much parasitic resistance. Where is it coming from? You ran your…