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Case Studies in P&R Double Patterning Debug: Part Two

Case Studies in P&R Double Patterning Debug: Part Two

David Abercrombie continues his expert advice to P&R and chip finishing engineers on understanding and debugging multi-patterning errors accurately and…

Case Studies in Double-Patterning Debug: Part One

Case Studies in Double-Patterning Debug: Part One

By David Abercrombie, Mentor Graphics Multi-patterning errors in P&R layouts can be intricate, and their solutions may not be obvious

The Changing (and Challenging) IC Reliability Landscape

The Changing (and Challenging) IC Reliability Landscape

By Matthew Hogan, Mentor Graphics Reliability issues have gone way beyond DRC and LVS verification…

The Fill Ecosystem Evolves Again

The Fill Ecosystem Evolves Again

By Jeff Wilson, Mentor Graphics At 20nm, new fill constraints drive up the time and complexity of the fill process….

Automate those voltage-dependent DRC checks!

Automate those voltage-dependent DRC checks!

By Beth Martin with Dina Medhat, Mentor Graphics  What do all these new voltage-dependent DRC rules mean, and how do…

Video: ECO Fill Flow Framework

Video: ECO Fill Flow Framework

A video introduction to Mentor’s newly introduced utility called ecofill.

Extraction Challenges Grow in Advanced Nanometer IC Design

Extraction Challenges Grow in Advanced Nanometer IC Design

By Carey Robertson, Mentor Graphics The Calibre xACT platform is a new type of extraction tool that provides a range…

Automated Chip Polishing Can Make Your Design Shine

Automated Chip Polishing Can Make Your Design Shine

By Bill Graupp, Mentor Graphics A more robust design creates a more reliable product, and reduces yield variability over its…

Are Three Eyes Better Than Two?

Are Three Eyes Better Than Two?

By David Abercrombie, Mentor Graphics Error analysis in triple patterning is challenging, but a pyramid approach helps designers prioritize and…