Latest posts

The virtuous cycle of silicon: How Siemens is accelerating the era of Physical AI with NVIDIA cuLitho

GPU-accelerated computational lithography with Siemens Calibre and NVIDIA cuLitho By Dr. Jim Shiely, Chief of Staff for Calibre Semiconductor R&D,…

Top-level schematic of a CMOS Low Dropout voltage regulator. An error amplifier (OA1) drives the gate of a PMOS pass transistor. The critical connection between the amplifier output and the transistor gate is labeled as the "VICTIM" net. The circuit also shows feedback resistors and an output capacitor.

Eliminating the silent killer of analog reliability: A structural approach to floating nets

By Bhanu Pandey, Product Engineer, Calibre Design Solutions A successful first silicon run starts with getting the design details right….

Solving the extraction challenges of CFET and backside power

By Karen Chow, Sheetal Veronica, and Kunjesh Agashiwala Introduction: The vertical evolution of semiconductor architecture Both complementary field-effect transistor (CFET)…

How shift-left memory contention analysis protects performance and schedule

Detect memory contention at the schematic level, optimize memory design and improve reliability with Insight Analyzer—advanced analysis for complex memory blocks

Manufacturing Intelligence: AI in the Fab

Discover how AI is fundamentally transforming semiconductor manufacturing, moving beyond traditional limits. Learn how AI tightens feedback loops, tackles bottlenecks, and orchestrates fab operations for unprecedented efficiency and innovation.

Why curvilinear OPC demands a new optimization approach 

The semiconductor industry’s transition to sub-5 nm nodes has fundamentally changed photomask design economics. For years, teams relied on rectilinear…

From chaos to clarity: Smarter DRC workflows and team productivity with Calibre Vision AI 

Advanced node DRC demands rapid team coordination and closure. You can transform your entire DRC workflow by turning massive error data into…

DRC at scale: How Calibre Vision AI turns billions of errors into actionable insights 

Accelerate DRC closure for advanced node SoCs with Calibre Vision AI. Real-time, AI-guided analysis shortens debug cycles and enables efficient team collaboration for faster, predictable physical verification.

Interactive symmetry checking with Calibre RealTime accelerates analog IC design

Learn how Calibre RealTime enables interactive symmetry checking in analog IC design with instant validation, zero setup and early detection to compress schedules and reduce costly rework