Latest posts

Using a shift left strategy to address block/chip design challenges during design-stage verification

By David Abercrombie For IC designers, striking the right balance between tight deadlines and limited resources is a constant challenge….

How to get accurate inductance extraction for superconductor ICs

By Hossam Sarhan and Dusan Petranovic Supporting the high performance and reliability needed for artificial intelligence (AI), data centers and…

The secret to Calibre software quality – AnaCov, our in-house code coverage analysis tool

By Mustafa Naeem, Ahmed Tahoon, Omar Ragi, and Reem El-Adawi In the realm of software testing, accurately tracking and analyzing…

Unraveling the 3DIC shift left strategy: Navigating the world of multi-dimensional ICs

By John Ferguson IC design’s evolution continues to push the boundaries of Moore’s law to new heights. One of the…

Mastering parasitic extraction at the 3 nm process node

By Dilan Heredia and Karen Chow Designing integrated circuits (ICs) for the 3 nm process node poses challenges never seen…

Why PID issues matter to IC chip designers, and how to combat them

By Derong Yan Integrated circuit (IC) chip designers are constantly striving to meet ever-increasing standards of reliability and performance in…

Shifting left with Calibre solutions: Enhancing IP design flow efficiency and design quality

By Terry Meeks Designing integrated circuits (ICs) is a multifaceted task that requires the integration of various components, including intellectual…

Revolutionizing software testing: Introducing TCP-Net++

By Mohamed Abdelkarim and Reem El Adawi In the dynamic world of software development, balancing speedy delivery with quality assurance…

ERC softchk features

Streamlining IC design verification with Calibre nmLVS Recon

By Kesmat Shahin As integrated circuits (ICs) become more complex, meeting tapeout schedules has become increasingly challenging. Statistics from industry…