Design with Calibre

The industry-leading Calibre toolsuite provides physical verification (DRC), circuit verification (LVS, PEX), and reliability verification (PERC), as well as Calibre DFM optimization, to ensure IC designs will deliver the power, performance, and foundry yield today’s markets demand. Across all process nodes and design styles, innovative functionality ensures the Calibre toolsuite provides accurate, efficient, comprehensive IC verification while minimizing resources and tapeout schedules.

Latest posts

Using Calibre eqDRC Verification Methodology for Curved Layouts in Silicon Photonics

January 16, 2017

Calibre eqDRC enables SiP designers to accurately verify non-Manhattan shapes in SiP designs.

By Design With Calibre

< 1 MIN READ

Are You (Really) Ready for Your Next Node?

January 11, 2017

By Michael White, Mentor Graphics Skipping nodes is gaining popularity, but it can bring some unexpected challenges. Are you prepared?

By Design With Calibre

6 MIN READ

How to use different Calibre versions for Calibre RealTime and signoff Calibre DRC/LVS jobs

January 10, 2017

In this How-To Video – learn how to run Calibre DRC and LVS jobs from a signoff Calibre version simultaneously…

By Design With Calibre

< 1 MIN READ

How to run multiple Calibre RealTime jobs using multiple rule-decks

January 3, 2017

Need to run multiple rule decks on an AMS design? The Calibre RealTime tool lets you do just that easily…

By Design With Calibre

< 1 MIN READ

A Pattern of Success: Calibre Pattern Matching

December 21, 2016

Calibre Pattern Matching enables innovative DRC and other applications across all process nodes and designs.

By Design With Calibre

< 1 MIN READ

How to run Calibre PERC jobs using Calibre Interactive

December 20, 2016

Running Calibre PERC jobs from the Calibre Interactive interface tool only requires a few easy steps. Get the details in…

By Design With Calibre

< 1 MIN READ

How to include additional rule files in Calibre Interactive

December 14, 2016

Want to run custom checks simultaneously with signoff DRC? The Calibre Interactive interface lets you do just that. Learn how…

By Design With Calibre

< 1 MIN READ

A new path for analog design constraints verification

December 12, 2016

By Dina Medhat, Mentor Graphics Accurate verification of explicitly-defined analog design constraints is crucial for reliability and performance.

By Design With Calibre

5 MIN READ

Mentor’s Battle of the Photonic Bulge

December 8, 2016

By Mitch Heins If silicon photonics verification is a battle to be won, Mentor Graphics is on the front lines…

By Design With Calibre

5 MIN READ