Latest posts

Back-annotating DFM enhancements to place & route tools

Back-annotating DFM enhancements to place & route tools

By James Paris, Mentor Graphics Back-annotation of DFM enhancements to P&R simplifies iterations as designers close timing and physical verification

Device Pin-Specific Property Extraction For Layout Simulation

Device Pin-Specific Property Extraction For Layout Simulation

By Phil Brooks, Mentor Graphics Can you accurately extract device pin-specific properties without creating phantom nets?  

Synthesis of Design Rules and Patterns

Synthesis of Design Rules and Patterns

By Michael White, Mentor Graphics Integrating pattern matching with design verification and process development yields benefits at all nodes. Learn…

Electromigration protection requires accurate interconnect modeling

Electromigration protection requires accurate interconnect modeling

By Karen Chow, Mentor Graphics Electromigration can destroy an IC before its time. Are your designs safe?

Leveraging Reliability-Focused Foundry Rule Decks

Leveraging Reliability-Focused Foundry Rule Decks

By Matthew Hogan, Mentor Graphics Using your foundry’s reliability rule deck early on lets you correct reliability issues while they…

Pattern Matching In Test and Yield Analysis

Pattern Matching In Test and Yield Analysis

By Jonathan Muirhead and Geir Eide, Mentor Graphics Analyzing fail data with pattern matching helps companies identify yield limiters faster…

Reliability Scoring for the Automotive Market

Reliability Scoring for the Automotive Market

By Jeff Wilson, Mentor Graphics Companies designing automotive electronics must understand how variability affects design quality and reliability.

Not yet a fan of fan-out? Why you should be!

Not yet a fan of fan-out? Why you should be!

By John Ferguson, Mentor Graphics FO-WLP combines multiple die from heterogeneous processes into a compact package, and that’s a good…

Interconnect Robustness Depends on Scaling for Reliability Analysis

Interconnect Robustness Depends on Scaling for Reliability Analysis

By Matthew Hogan, Mentor Graphics Fast simulation and PEX are both crucial to interconnect robustness verification. Can your tools scale…