Design with Calibre

The industry-leading Calibre toolsuite provides physical verification (DRC), circuit verification (LVS, PEX), and reliability verification (PERC), as well as Calibre DFM optimization, to ensure IC designs will deliver the power, performance, and foundry yield today’s markets demand. Across all process nodes and design styles, innovative functionality ensures the Calibre toolsuite provides accurate, efficient, comprehensive IC verification while minimizing resources and tapeout schedules.

Latest posts

GIGO, or Why Data Integrity Matters

September 11, 2017

By James Paris – Mentor, A Siemens Business Design data integrity is crucial to both product quality and tapeout schedules….

By Design With Calibre

2 MIN READ

Node Migration—What Does it Really Cost You?

September 1, 2017

By John Ferguson – Mentor, A Siemens Business Deciding when and how to make a process node transition is critical…

By Design With Calibre

2 MIN READ

CMP Modeling: Improving Manufacturing Results during Design

August 28, 2017

By Jeff Wilson and Ruben Ghulghazaryan – Mentor, A Siemens Business Accurate CMP models and simulation are crucial to both design process…

By Design With Calibre

3 MIN READ

The Speed of Reliability

August 22, 2017

By Dina Medhat – Mentor, A Siemens Business Electrical overstress (EOS) can damage or destroy an IC. The Calibre PERC…

By Design With Calibre

3 MIN READ

No Compromise: Fast, Accurate Parasitic Extraction at Advanced Nodes

August 14, 2017

By Chris Clee – Mentor, A Siemens Business Calibre’s innovative hybrid approach to parasitic extraction can solve your PEX challenges…

By Design With Calibre

2 MIN READ

In-Design Signoff DRC: Not Just a Dream

July 25, 2017

By Srinivas Velivala – Mentor, A Siemens Business Are you a custom or analog/mixed signal (AMS) designer? How often do…

By Design With Calibre

2 MIN READ

Searching for Latch-up in All the Right Places

July 17, 2017

By Matthew Hogan – Mentor, A Siemens Business While any error in a layout could be deemed unintentional (I mean, who…

By Design With Calibre

2 MIN READ

Take the Risk out of Signoff with Calibre YieldEnhancer Chip Polishing

July 10, 2017

By Bill Graupp – Mentor, A Siemens Business Designing integrated circuits (ICs) today is a complex and high-risk endeavor…

By Design With Calibre

3 MIN READ

Okay, I released my design to the fab, now what? Design to Mask – Part 2

July 5, 2017

By Minghui Fan – Mentor, a Siemens Business Managing the computational demands of today’s OPC and RET takes a dedicated…

By Design With Calibre

5 MIN READ