By Matthew Hogan – Mentor, A Siemens Business
Custom reliability verification? No reliability verification? Foundry-qualified reliability rule decks provide an excellent foundation for establishing baseline robustness and reliability criteria.
For many IC design and IP companies, reliability verification is a new area, one with heightened visibility and different demands. Reliability initiatives such as the TSMC9000 IP quality program, ISO 26262 functional safety standard for automotive components, and RESCAR automotive reliability checks, are driving new attention to the reliability issues that can impact circuit performance and product lifetime.
As a result, many companies are integrating reliability checking into their verification flows. Fortunately, foundries have also recognized the importance and value of reliability verification, and responded by creating qualified reliability rule decks. These rule decks provide a baseline for reliability verification that the design companies can trust, knowing it has been thoroughly vetted by the foundry in the same way that DRC and LVS decks are.
Of course, there are a few considerations to be, well, considered as you establish your reliability verification flows. Because each foundry typically has a different reliability focus, it is important to understand what’s covered by your foundry’s reliability rule deck—even more so if you’re one of those companies that uses multiple foundries. Take the time to review the contents with your reliability/ESD team, and understand how well-aligned the foundry rules are with your own internal requirements, flows, and design practices. You might find you’ll need to make a few additions or modifications to ensure any proprietary requirements are covered.
Adopting foundry-provided reliability design rules, whether it’s part of transitioning to a new process node, or integrating the rules into an established node, is a project many companies choose to implement incrementally. They often start by supplementing whatever in-house reliability verification methodologies and rule checks they already have with some of the checks from the foundry rule deck. Starting small, gaining trust in the process and the results, then transitioning more and more of the design flow to foundry-provided reliability rule decks is a typical evolutionary path.
Whatever implementation approach you take, there are two important use models every company should include in reliability verification:
- IP/block validation—verify your IP and blocks early and often, whether they are from internal or 3rd-party suppliers. Validating IP/block reliability at each level as you select and build up the design provides a deterministic path to success as you move towards consideration of these design elements in the context of the whole chip.
- Full-chip verification— overall chip context is essential when validating critical reliability applications such as ESD and EOS protection, voltage-aware DRC spacing, and interconnect robustness (particularly critical for avoiding CDM issues by ensuring low resistance between ESD clamps).
Foundry reliability rule decks used for both IP and full-chip runs usually have settings or modes that define the verification level needed to create the appropriate results.
Ensuring consistent, complete, and accurate reliability verification solutions is a critical step for ensuring long term device performance and product lifetime. Foundry-qualified and foundry-maintained reliability rule decks enable design and IP companies alike to establish baseline robustness and reliability criteria without committing extensive time and resources for the creation and support of proprietary verification solutions.
If you’d like to learn more, read my latest white paper, Jumpstart your reliability verification with foundry-supported rule decks, or check out the Calibre® PERC™ reliability platform. With an extensive set of foundry-qualified and foundry-maintained reliability rule decks available, the Calibre PERC platform provides a wide range of automated checking capabilities focused on finding and resolving today’s complex reliability challenges.