A look at what’s to come at OIP (hint: we’ll be there!)

By Design With Calibre

The 2018 TSMC Open Innovation Platform® (OIP) Ecosystem Forum in Santa Clara starts this Wednesday, October 3rd! As usual, Mentor is delighted to have a strong presence throughout the OIP activities, highlighting the long-standing and ongoing collaboration and cooperation between TSMC and Mentor.

In collaboration with our mutual customers, Mentor experts will be presenting four papers:

  • AMD Adoption of Calibre 3DSTACK for CoWoS and InFO Style Design Verification
    by AMD and Calibre
  • Customer Success Story: Improving Circuit Reliability with Calibre PERC – AMD Collaboration with Mentor for ESD/Latch-Up Solution
    by AMD and Calibre
  • Silicon-accurate Mixed-Signal Verification of 7nm PLL IP for 100GB Applications
    by Analog Bits and IC Verification Solutions &Analog/Mixed-Signal
  • Designing Ultra-smart IoT Edge Devices using TSMC Technologies
    by SoftMEMS and Tanner

Over in the Partners Pavilion, look for our exhibit highlighting our Calibre, Tessent, BSD (Board Systems Division), and Analog/Mixed-Signal products. Have questions? Want to check out the latest functionality? Stop by and talk to one of our experts, watch a demo, or pick up some literature.

We’re especially excited to announce that Mentor will be receiving two Partner of the Year Awards at OIP! The following awards will be presented at the VIP lunch during OIP:

  • Joint Development 5nm Design Infrastructure
  • Joint Delivery of WoW Design Solution

During the OIP Forum, TSMC will announce EDA tool readiness and PDK readiness for 5nm and 7nm Plus FinFET processes. In conjunction, Mentor will announce the extension of their solutions in support of these process technologies.

For more details on the event, visit TSMC’s website for a full agenda of activities! We hope to see you there!

Leave a Reply

This article first appeared on the Siemens Digital Industries Software blog at