By Karen Chow and Claudia Relyea – Mentor, A Siemens Business
Parasitics hampering the performance of your advanced node or 3D-IC designs? The Calibre xACT solution helps you find and solve the toughest parasitic conditions quickly and accurately.
Can you hear hordes of parasitics crawling through your design layouts? Do you lie awake wishing you could just get rid of them all? Advanced node designs and 3D-IC packages are presenting a variety of new and complex parasitic issues to designers. FinFETs, FD-SOI, and GAA transistors extend gate scaling, but generate increased parasitic interactions between neighboring geometries. 3D-IC promises to provide device scaling while minimizing cost, but requires verification of parasitic effects between components and interconnect on multiple processes.
Some design companies have adopted changes to their design methodologies in an effort to reduce parasitic effects, but a more long-term solution is a comprehensive approach that includes extensive interconnect modeling and extraction, combined with enhanced design analysis. After all, if you don’t know where the next parasitic is coming from, isn’t it better to have an eradication strategy that can handle anything that comes along?
The Calibre® xACT™ solution offers accurate capture of parasitic and layout-dependent effects for non-planar devices in interconnect modeling, accurate extraction and modeling for 3D-IC designs, and netlist input for downstream analysis. Simultaneous multi-corner extraction handles complex modeling requirements with efficient processing, while providing device location information to the EM/self-heating analysis ensures current density violations can be accurately identified and resolved.
If you’re ready to realize the performance and market benefits of your advanced node and/or 3D-IC designs, you should check out our white paper, Parasitic Extraction Technologies for Advanced Node and 3D-IC Design. It’ll help you exterminate the parasitics you see, and the ones you never knew existed.