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The “Standards Corner” Becomes a Blog

The “Standards Corner” Becomes a Blog

While I have spent a decade sharing the developments of EDA standards with you monthly in the ModelSim Informant and…

I Am Honored to Honor

I Am Honored to Honor

IEEE Charles Proteus Steinmetz Award I am honored to chair the IEEE Charles Proteus Steinmetz Award 2010 committee for selection…

IEEE Standards Association Awards Ceremony

IEEE Standards Association Awards Ceremony

Congratulation Peter! At the December 5, 2009 IEEE SA Awards Ceremony, the “Ron Waxman Design Automation Standards Committee (DASC) Meritorious…

ABV and being from Missouri…

ABV and being from Missouri…

The last industry project I worked on, before joining EDA, was an advanced chip set for a very large, high-end…

Time hogs, blogs, and evolving underdogs…

Time hogs, blogs, and evolving underdogs…

I realized a few years back that “time” is an engineer’s most precious resource. It seems that there’s just never…

Full House – and this is no gamble!

Full House – and this is no gamble!

SystemVerilog proved to be a “royal flush” of a reason for 100’s of people to gather together. Leaving poker references…

Welcome to the Verification Horizons Blog!

Welcome to the Verification Horizons Blog!

Hi Everyone, As Editor of the Verification Horizons newsletter, it is my pleasure to welcome you to the newest facet…

SystemVerilog: The finer details of $unit versus $root.

SystemVerilog: The finer details of $unit versus $root.

Another installment of “Longwinded Answers to Frequent SystemVerilog Questions: $root versus $unit” Believe me – I tried to make this…

SystemVerilog Coding Guidelines

SystemVerilog Coding Guidelines

I have lots of blog entries about 95% ready to publish. This entry is from an e-mail I wrote a…