Just wanted to let you all know that the new issue of Verification Horizons is now available. You can get the full edition online at the Verification Academy. Please be sure to check it out. There are a few articles in particular that I’d like to call your attention to.
Using Formal Analysis to “Block and Tackle” by Paul B. Egan of Rockwell Automation is a great case study in how apply formal to reduce verification time at both the block and chip level by plugging coverage holes missed by simulation. In the article, Paul describes a straightforward three-step process to add formal analysis to your verification flow.
In Bringing Verification and Validation under One Umbrella my colleagues Hemant Sharma and Hans van der Schoot present a unified flow for RTL verification and pre-silicon validation of hardware/software integration by reusing your transaction-level testbench from simulation to emulation.
Be sure the check out The Evolution of UPF: What’s Next? by Erich Marschner. Erich is the chair of the IEEE 1801 committee, which just released UPF 2.1, so there is no one better to explain the new features in this latest release. You can also read about the evolution of features in UPF from 1.0 to 2.1 in a previous issue of Horizons here.
Our friends at CVC list the Top Five Reasons Why Every DV Engineer Will Love the Latest SystemVerilog 2012 Features, and Mark Litterick of Verilab (and recent Best Paper winner at DVCon 2013 – congratulations!) shares his experiences of OVM-to-UVM migration in OVM to UVM Migration, or “There and Back Again: A Consultant’s Tale.”
We’re already working on our DAC edition of Verification Horizons, so if you’d like to submit an article, we’d love to have you.