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ABV and being from Missouri…

ABV and being from Missouri…

The last industry project I worked on, before joining EDA, was an advanced chip set for a very large, high-end…

Time hogs, blogs, and evolving underdogs…

Time hogs, blogs, and evolving underdogs…

I realized a few years back that “time” is an engineer’s most precious resource. It seems that there’s just never…

Full House – and this is no gamble!

Full House – and this is no gamble!

SystemVerilog proved to be a “royal flush” of a reason for 100’s of people to gather together. Leaving poker references…

Welcome to the Verification Horizons Blog!

Welcome to the Verification Horizons Blog!

Hi Everyone, As Editor of the Verification Horizons newsletter, it is my pleasure to welcome you to the newest facet…

SystemVerilog: The finer details of $unit versus $root.

SystemVerilog: The finer details of $unit versus $root.

Another installment of “Longwinded Answers to Frequent SystemVerilog Questions: $root versus $unit” Believe me – I tried to make this…

SystemVerilog Coding Guidelines

SystemVerilog Coding Guidelines

I have lots of blog entries about 95% ready to publish. This entry is from an e-mail I wrote a…

The Language versus The Methodology

The Language versus The Methodology

I’ve been around simulation and synthesis languages for a while; back when you needed an NDA to see the Verilog…

Are Program Blocks Necessary?

Are Program Blocks Necessary?

That’s a frequent SystemVerilog question I’m asked. Program blocks came directly from donation of the Vera language to SystemVerilog by…