Announcement: Siemens EDA are excited to announce availability of our Verification IP products for UCIe version 2.0, coincident with today’s…
As the saying goes: Those who fail to plan, plan to fail. With that said, I am excited to announce…
23rd Synopsys EDA Interoperability Forum Features a Verification Session with focus on the UVM Register Package As readers of the…
United States Plays Host in Seattle, WA The IEC’s 47th General Assembly meeting opened on October 11th in Seattle, WA…
Technorati Tags: UVM,SystemVerilog,RAL,OVM The development of UVM in the Accellera VIP-TSC brings up, yet again, the age-old philosophical question: should…
UVM is Taking Shape While you have all been happily verifying your complex SoCs the Accellera VIP Technical Subcommittee (VIP-TSC),…
Mentor/Synopsys Collaboration Bears Fruit Two weeks back I shared information in a blog on collaboration between Mentor Graphics and Synopsys…
Companion OVM Cookbook Examples Kit also offered for download Several months ago, the OVM Cookbook and the Examples Kit were…
Mentor Announces Collaboration with Synopsys on Joint Register Package Candidate Mentor has recently teamed with Synopsys to collaborate on the…
In my last blog, I gave a few examples of different ways of thinking about getting more work done by…
