Semiconductor Packaging

Monolithic scaling limitations drive the growth of 2.5/3D multi-chiplet, heterogeneous integration that enables PPA targets to be met. Our integrated flow addresses prototyping challenges to signoff for FOWLP, 2.5/3D IC, and other emerging integration technologies.

Learn more about semiconductor packaging design and verification.

Latest posts

Image of chiplets with text onscreen saying HBM

High Bandwidth Memory (HBM): Unleashing the power of next-gen memory technology

September 28, 2023

In the ever-evolving realm of semiconductor technology, one innovation stands out above the rest: High Bandwidth Memory (HBM). Offering unparalleled…

By Edward Hudson

3 MIN READ

What’s new in Xpedition IC Packaging VX.2.14

September 19, 2023

The new VX.2.14 release of Xpedition IC Packaging includes improvements and enhancements to both Xpedition Substrate Integrator and Xpedition Package…

By Keith Felton

2 MIN READ

SemiWiki Podcast – An expert panel discussion on the move to chiplets

September 13, 2023

Listen in as Tony Mastroianni Advanced Packaging Solutions Director – Siemens EDA along with Saif Alam Vice President of Engineering…

By John McMillan

< 1 MIN READ

Shifting left with system technology co-optimization for IC packaging

August 17, 2023

We have witnessed and learned about the industry’s significant shift in semiconductors. The traditional approach of transistor scaling, once universally…

By Keith Felton

3 MIN READ

A workflow methodology for homogeneous disaggregation using hierarchical device planning

July 20, 2023

Advancements in IC packaging manufacturing, combined with the exploding costs of designing monolithic ICs on today’s advanced process nodes, have…

By Chris Cone

5 MIN READ

A “big rock” approach to DC drop analysis in IC package design

June 15, 2023

The key analysis needs of high-performance computing semiconductor package design Today, power requirements are continually increasing as you bring more…

By Steve McKinney

4 MIN READ

Why are you spending 30%+ more time on semiconductor packaging design?

May 18, 2023

Designs are just getting bigger and more complex Yes, an obvious aspect is increasing design complexity. Packages are now a…

By Keith Felton

2 MIN READ

Why co-design-driven semiconductor package planning and prototyping is critical for design success

April 20, 2023

The connectivity management complexity of package assemblies where multiple chiplets/ASICs and memory are heterogeneously integrated, introduces a great deal of…

By Keith Felton

3 MIN READ