Are you a C++ developer or programmer? You may want to read this…

By day, Fedor Pikus is head of the Advanced Projects Team in Siemens Digital Industries Software. His responsibilities include planning…

Introducing Calibre DesignEnhancer design-stage layout optimization!

By Jeff Wilson Introduced in early 2023, the Calibre DesignEnhancer tool is part of a growing suite of shift-left tools…

What’s all the fuss about shift left?

By Michael White and David Abercrombie In recent months, it seems as though everyone’s been talking about shift left as…

Why take chances with your PV job setups when a winning alternative is available?

By Richard Yan Are you interested in optimizing your integrated circuit (IC) physical verification (PV) flows? How does automating the…

How can I run reliability checks early in the design cycle?

By Hossam Sarhan and Alexandre Arriordaz With the increasing complexity of design layouts and shorter tapeout cycles, waiting until signoff…

ERC softchk features

The secret superpower of early design verification

By Kesmat Shahin How many times, as you traversed across design stages and ran countless iterations, have you wished that…

A software migration that improves productivity? The Calibre Interactive tool has a (new) GUI for that…

By Slava Zhuchenya Software migration can be a dreaded endeavor, especially for electronic design automation (EDA) tools that design companies…

Find high resistance faster in P2P violations with interactive P2P analysis

By Slava Zhuchenya So your net trace has too much parasitic resistance. Where is it coming from? You ran your…

Fast, efficient, productive? Your early-stage IC design physical verification can be all that…

By John Ferguson and Nermeen Hossam With each new process node comes more complex requirements needed to ensure working silicon. …