Introduction What happens when you start your simulation with a UVM test bench? Where should you put the uvm_config_db::set() calls…
Where can you improve your verification skills? In March 2023 I attended DVCon US, the Verification and Design Conference in…
What are Large Language Model’s hallucinations. LLMs will be powerful EDA productivity tool once we know what caused it and how to deal with their adverse effects.
Please mark your calendars for the highly anticipated 60th anniversary Design Automation Conference (DAC). The 60th DAC will take place…
I can’t take credit for the great flowers in the garden. It’s the tremendous rain we’ve had in California this…
Introduction In a previous post, I said that in SystemVerilog, once you specialize a class, you can not make a…
Some of you may have wondered for the past few years why we chose to use the name Verification Horizons…
The importance of verification data learned from training Large Language Models. In DVCon will share an overview of ML applications in verification and . present VIQ tutorial on how data can empower verification, with demos of existing ML applications.
1 – The Tuesday keynote For the first F2F/IRL DVCon since 2020, the Steering Committee wanted a fresh alternative to…
