Reminder: DVCon U.S. 2026 Call for Papers – Sept 7th Deadline Approaching!
The DVCon U.S. 2026 Call for Papers deadline is Sunday, September 7th at 11:59 PM. Don’t miss your chance to share your expertise and help shape the future of design and verification.
What’s New This Year?
DVCon U.S. 2026 will be held at a new, larger venue – the Hyatt Regency Santa Clara – from March 2–5, 2026. There will be more space, more networking, and more opportunities to showcase your work!
Topic Categories Include:
- Verification & Validation – Methodologies, testbenches, coverage, and more.
- Design & Modeling – RTL, high-level design, and modeling techniques.
- Formal Methods – Property checking, equivalence checking, and formal verification.
- Low Power Design & Verification – Techniques for energy-efficient systems.
- Mixed-Signal Design & Verification – Bridging analog and digital worlds.
- Functional Safety & Security – Safety-critical systems and secure design.
- Standards & Interoperability – UVM, SystemVerilog, SystemC, and beyond.
- Emerging Trends – New paradigms and methodologies shaping the future.
Notice something missing? There’s no dedicated AI/ML category. But don’t let that stop you! If your neural net dreams of closing coverage gaps or your LLM wants to write assertions, we want to hear about it. Just tie it to an existing category—AI for low-power optimization? ML for formal property generation? Go for it! (Just don’t let your AI submit the paper for you… yet.) [Disclaimer– I asked GPT-5 to help write that last paragraph🤓]
Hope to see you in person March 2-5, 2026 in Santa Clara,CA,
Dave Rich
DVCon US 2026 Program Chair
Functional Design and Verification Learning Services
