formal - Verification Horizons

With last year’s acquisition of OneSpin, we now have a valuable addition to the solutions I described in The Many…

The sight of kids going back to school can prompt feelings of joy and renewal – or trigger less pleasant…

On the short list of positive things to come out of the past year are the formal verification-focused conference papers…

As I noted at the beginning of this series, the term “logic equivalence checking” (LEC) applies to a number of…

[Preface / reminders: Part 1 of this series focused on synthesis validation with LEC and SLEC, Part 2 describes how…

[Preface / reminders: Part 1 of this series focused on synthesis validation with LEC and SLEC, and Part 2 describes…

[Preface: I briefly interrupt my series on The Many Flavors of Equivalence Checking to share this report on an important…

In EDA, the word “simulation” is used everywhere: there is RTL and gate level simulation, analog simulation, RF simulation, and…

We hope to see you at DVCon U.S. 2018. Mentor will showcase 17 papers and posters during the conference on…