Siemens at DVCon India 2025: Driving the Future of Design and Verification
DVCon India 2025, taking place on September 10–11 at the Radisson Blu, Marathahalli, Bengaluru, will mark a special milestone—its 10th anniversary. Over the past decade, DVCon India has grown into one of the region’s most influential conferences for design and verification professionals. Siemens will be prominently featured across vision talks, technical papers, posters, and workshops, showcasing its leadership in AI-driven EDA, hardware-assisted verification, and formal methodologies.
Conference Theme: Architecture to Analytics (A2A)
The conference continues last year’s theme – Architecture to Analytics – to emphasize the convergence of design architecture and data-driven verification strategies. Attendees will explore how analytics, AI, and intelligent automation are transforming the entire design lifecycle, from early architectural decisions to post-silicon validation. Siemens’ contributions will align closely with this theme, highlighting innovations that bridge design intent with verification intelligence.
🧠 Vision Talk
- Software-defined Hardware Design Relies on AI and Intelligent Verification
🗣️ Jean-Marie Brunet, VP & GM HW Assisted Verification, Siemens
📅 Sept 10 | 🕤 09:30–10:15 | 📍 Grand Victoria
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This visionary talk will explore how AI is reshaping hardware design and verification, enabling dynamic optimization and runtime adaptability.
📄 Technical Paper
- Pumping Up Test Development with Task-Based, C-callable UVM-based Tests
👨💻 Authors: Rich Edelman, Didan Francis
📅 Sept 11 | 🕧 12:45–13:15 | 📍 Track 1 – Grand Victoria B
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This paper will present a practical approach to integrating C-callable tasks into UVM testbenches, streamlining test development and reuse.
🧪 Poster Presentations
- Beyond Traditional Testing: Integrating DV and DFT for Zero-Defect Goals
👥 Authors: Jyothy Melaedavattil Jaganathan, Ann Keffer, Gaurav Goel
📅 Sept 11 | 🕚 11:30–16:30 | 📍 Exhibit Area
– - Next-Generation CDC and RDC Closure: An AI/ML-Driven Approach
👥 Authors: Ravi Pathak, Abdul Moyeen
📅 Sept 11 | 🕚 11:30–16:30 | 📍 Exhibit Area
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These posters will highlight Siemens’ innovations in integrating design-for-test with verification and applying AI/ML to constraint generation.
🧠 Workshops & Tutorials
- Verify Your Next AI/ML Design with Questa One Avery VIP
👨💻 Author: Ankit Garg
📅 Sept 10 | 🕚 11:30–12:15 | 📍 Track 3 – Robusta & Arabica
– - Power Dynamics: Shaping the Future of the Data-Centric Era and the Role of AI
👨💻 Author: Vijay Chobisa
📅 Sept 10 | 🕚 11:30–12:15 | 📍 Track 5 – Shao
– - Achieve Software Prototyping Verification Success with Veloce proFPGA CS
👩💻 Author: Marshneil Koul
📅 Sept 10 | 🕧 12:15–13:00 | 📍 Track 2 – Grand Victoria A
– - Unleashing the Potential of Agentic AI Within Design & Functional Verification
👨💻 Author: Mark Carey
📅 Sept 10 | 🕓 16:45–17:30 | 📍 Track 3 – Robusta & Arabica
Our presence at DVCon India 2025 reflects our deep commitment to advancing the state of verification and design automation. Team Siemens attendees will highlight solutions that span simulation, emulation, formal, and AI-enhanced methodologies. These sessions will offer insights into how Siemens helps customers accelerate time-to-market, improve design quality, and scale verification across increasingly complex SoCs. Attendees will gain a firsthand look at how Siemens enables the future of intelligent, software-defined hardware design.
I look forward to connecting with colleagues across the industry in person at DVCon India. The conference offers a unique opportunity to engage with both established and emerging companies in the expo area, exchange ideas, and explore collaborative opportunities that advance the electronic design automation ecosystem—not just with Siemens, but with the broader design and verification community. This year sees a record number of exhibitors and the DVCon India team has worked hard to accommodate each of them. See you there!
