The importance of simulation in the pursuit of absolute speed!
I recently had an opportunity to talk to someone who worked in the high-frequency trading (HFT) sector a few years ago. I wanted to know how they performed their functional simulations. If you know anything about HFT or low-latency trading, you know that those engineers are very secretive and don’t divulge a lot of details about what their FPGA design-verification process entails. So having this conversation with an ex-insider was very interesting and gave me a better perspective of what kind of challenges they have in their FPGA designs.
Surprising Revelations
The first thing that surprised me was that only the bigger firms have the resources to run a full team of verification engineers who can leverage the latest verification methodologies like UVM. Some firms rely on CocoTB and use it in conjunction with their commercial simulator to generate complex tests for designs. But what surprised me the most was that a lot of firms just run some sanity checks on their code using a free simulator and then program the board and test it on the actual hardware!
As someone who has spent all my career in a field surrounding RTL simulation, it was really shocking to me that firms in the HFT sector, where every nanosecond counts, are risking not finding bugs early in the design process and thereby risking the chances of more code re-spins. Each re-spin is so costly in terms of time and effort needed by engineers, that by adding simulation in their workflow, they could significantly reduce the number of iterations of code changes to find a bug.
Simulation is Key
I do understand that getting into a commercial simulator is not an easy task. You’d need a verification engineer to lead that effort, learn some type of verification methodology and not to mention the cost of the commercial simulator. There are several ways to address this problem, the easiest way is to leverage CocoTB as the test environment. It is Python based and you don’t need a dedicated verification engineer who knows VHDL or SystemVerilog to lead that effort. This means if your firm already has software engineers, they can start writing tests in python!
Another way to look this problem is that you don’t really need a verification methodology like UVM to run simulations. There are a wide variety of methodologies that can suit you depending on what type of HDL language you are comfortable with, or in a lot of cases you don’t really need a methodology. This is because SystemVerilog has a lot of capabilities to run constrained random tests and collect functional coverage which can be done without using UVM. Of course, UVM gives you the ability to re-use test environments and ability to interface with VIPs, but you don’t have to jump into the deep end directly, there are ways to dip your toes slowly into the world of verification and slowly make your way up to the advanced verification methodologies.
This is why Questa Simulation has three different configurations. Each configuration has different capabilities and there’s the price consideration as well. The three configurations give you three different entry points, so depending on what your level of expertise is and depending on how complex you want your verification environment to be, you can pick the one that fits your needs best. But the most important feature that’s vital in any verification environment, a debugger, is included in all configurations of Questa Simulation. The Visualizer Debug Environment is the debug framework for simulation, static, formal, emulation, prototyping, analog and more. Visualizer helps users to easily debug any simulation mismatches using advanced features such as: time cone view, biometric search, transaction viewer, FSM view and more.
Learn More
I could go on and on about all the different ways Questa Simulation and Visualizer can help you Win the Tick to Trade Race, but I will leave that to the experts who can go more in detail of how these features work. If you are interested, our resident expert on Visualizer, Rich Edelman, is conducting a Live Webinar on April 16th, 2024, about Visualizer and how it can help the financial sector in optimizing their simulation flows. Please use the link below to register: Registration
