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2026 Siemens EDA and Wilson Research Group Functional Verification Study

The 2026 Functional Verification Study: Evidence of a New Verification Operating State

September 8, 2026

Explore key findings from the 2026 Siemens EDA and Wilson Research Group Functional Verification Study, including the latest trends, challenges, and priorities shaping functional verification.

By Harry Foster
3 MIN READ
Join Moses Satyasekaran at DVCon Taiwan on September 8 to explore how agentic AI could reshape design, verification, and the role of the engineer

Why Agentic AI Could Redefine the Future of Design and Verification

August 31, 2026

Discover how agentic AI is reshaping design and verification—and why the rise of the Design & Verification Scientist matters. Join Moses Satyasekaran at DVCon Taiwan on September 8 for a keynote exploring what comes next.

By Harry Foster
2 MIN READ
DVCon India 2026

The Verification Problem Is Changing. Are We Asking the Right Questions

August 24, 2026

DVCon India 2026

By Harry Foster
3 MIN READ

When thousands of RDC violations aren’t real: Making RDC verification smarter

July 17, 2026

Imagine opening your latest reset domain crossing (RDC) report after a long overnight verification run. The analysis completes successfully. That’s…

By Reetika
3 MIN READ
Siemens at DAC 2026

Discover What’s Next: Siemens EDA at DAC 2026

July 14, 2026

Join me at DAC 2026 to discover how Siemens EDA is advancing agentic AI, 3D IC, and software-defined systems—and shaping what’s next for semiconductor engineering.

By Harry Foster
3 MIN READ

Verification Academy 2026 webinar round-up

June 15, 2026

It’s hard to believe, but we’re already almost halfway through 2026! Time flies when you’re innovating, and here at Siemens,…

By Dennis Brophy
6 MIN READ
An image of an IC on a PCB

Verification IP: Why design teams buy instead of build

May 18, 2026

When we say verification IP, we mean pre-built verification solutions for standards-based peripheral interconnect interfaces and memories.

By Gordon Allan
5 MIN READ
DVClub Austin

Join Me at DVClub Austin — May 20, 2026

May 11, 2026

The End of Orthogonalization: Why Verification Is Entering a New Era The semiconductor industry is entering one of the biggest…

By Harry Foster
2 MIN READ

Why DFT Verification Signoff Is the Hidden Risk Threatening Your Next Tapeout

April 14, 2026

The Stakes Have Never Been Higher Today’s chips integrate billions of transistors, dozens of IP blocks, and deeply hierarchical architectures, all…

By Jake Wiltgen
3 MIN READ