system technology co-optimization

Shifting left with system technology co-optimization for IC packaging

We have witnessed and learned about the industry’s significant shift in semiconductors. The traditional approach of transistor scaling, once universally…

Image of an IC package design with text that says A workflow methodology for homogeneous disaggregation using hierarchical device planning

A workflow methodology for homogeneous disaggregation using hierarchical device planning

Advancements in IC packaging manufacturing, combined with the exploding costs of designing monolithic ICs on today’s advanced process nodes, have…

Illustration of an IC Package design with text that says Why are you spending 30%+ more time on semiconductor packaging design?

Why are you spending 30%+ more time on semiconductor packaging design?

Designs are just getting bigger and more complex Yes, an obvious aspect is increasing design complexity. Packages are now a…

Illustration of 3D IC design workflows

Why co-design-driven semiconductor package planning and prototyping is critical for design success

The connectivity management complexity of package assemblies where multiple chiplets/ASICs and memory are heterogeneously integrated, introduces a great deal of…

Image of a semiconductor package design

What are the top challenges of high-performance computing/AI semiconductor package design?

If you’re designing a high-performance processor-based package,  it’s common for the semiconductor package design to contain multiple logic chips that…

Illustration of a system-in-package (SiP)

How to get your system-in-packages right

People have been designing “modules” or system-in-packages (SiP) for a number of years; but in the last 3-5 years, I…