Why is a comprehensive workflow essential for chiplet design and today’s 3D IC architectures?
Moore’s Law, which has driven semiconductor industry growth for over 50 years, is reaching its physical limits. However, heterogeneous integration and various aggregation methods (such as SiP (System in Package), 2.5D, and true 3D stacking) offer new avenues to advance silicon technology for AI and high-performance computing.
What is driving chiplets?
The semiconductor industry is witnessing a trend toward larger chips, which leads to increased yield loss and design challenges. However, chiplet technology enables specialized optimization by combining different process nodes and sources. Chiplets allow us to mix and match geometries, optimizing each function’s performance. Additionally, die-to-die interface protocols like UCIe or HBM are crucial for electrical interaction between individual dies, and new pin floorplanning techniques are needed due to high pin counts.
What does the comprehensive chiplet integration workflow look like?
Chiplet design and today’s 3D IC architectures, in general, require a comprehensive workflow. Along with the traditional EDA validation steps including design for test, functional verification and SI/PI/EMI, we need to validate mechanical stress and thermal effects. All while managing the top-level floor planning, layout implementation and signoff DRC checking.
3D IC workflow steps
- Architecture
- Verification
- Place & Route
- Electrical analysis
- Mechanical integration
- Thermal & Stress
- DFT & Test
Leveraging shift-left technologies is essential to discovering architectural issues in the thermal, mechanical and electrical domains.
Key benefits for Siemens 3D IC design flow tools – scalable, flexibility, and ease-to-use – help designers optimize test technology resources
Digital Transformation for 3D Chip Design:
- Enable co-design, co-simulation, and automated system analysis.
- Replace manual interfaces with automated methods and defined workflows.
Comprehensive 3D IC Packaging Coverage:
- Validate performance and verify designs from predictive to final sign-off.
- Automated reviews catch issues early, reducing iterations.
Team-Based Design and Advanced Packaging:
- Support concurrent development and IP reuse.
- Utilize a single chiplet layout tool for organic and silicon substrates.
Siemens EDAs’ integrated IC packaging solution that covers everything from planning and prototyping to signoff for various integration technologies such as FCBGA, FOWLP, 2.5/3D IC, and others. Our IC packaging solutions help you overcome the limitations of monolithic scaling.
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Explore this infographic to learn why a comprehensive workflow essential for chiplet design and today’s 3D IC architectures
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