Why take chances with your PV job setups when a winning alternative is available?

By Richard Yan Are you interested in optimizing your integrated circuit (IC) physical verification (PV) flows? How does automating the…

How can I run reliability checks early in the design cycle?

By Hossam Sarhan and Alexandre Arriordaz With the increasing complexity of design layouts and shorter tapeout cycles, waiting until signoff…

ERC softchk features

The secret superpower of early design verification

By Kesmat Shahin How many times, as you traversed across design stages and ran countless iterations, have you wished that…

A software migration that improves productivity? The Calibre Interactive tool has a (new) GUI for that…

By Slava Zhuchenya Software migration can be a dreaded endeavor, especially for electronic design automation (EDA) tools that design companies…

Find high resistance faster in P2P violations with interactive P2P analysis

By Slava Zhuchenya So your net trace has too much parasitic resistance. Where is it coming from? You ran your…

Fast, efficient, productive? Your early-stage IC design physical verification can be all that…

By John Ferguson and Nermeen Hossam With each new process node comes more complex requirements needed to ensure working silicon. …

AUA announces extension of collaboration with Siemens for advanced research and academic enhancement

Back in 2012, the American University of Armenia (AUA) initiated a collaborative relationship with electronic design automation (EDA) leader Mentor…

Google, AMD, and Siemens EDA walk into a cloud…

By Michael White At DAC this past July, I had the opportunity to sit down with Phil Steinke from AMD…

What’s an ESD design window, and why do I care?

By Derong Yan As we move to advanced semiconductor process nodes, electrostatic discharge (ESD) issues have become more critical in…