A touchy subject: RF IC layout verification

By Neel Natekar Radio frequency (RF) circuitry is an essential component of many of the critical applications we now rely…

SAMP series finishes with SAMP cut mask decomposition techniques

By David Abercrombie and Rehab Kotb Ali – Mentor, A Siemens Business We’ve been writing about self-aligned multi-patterning (SAMP) topics…

ECO Fill Can Rescue Your SoC Tapeout Schedule

ECO Fill Can Rescue Your SoC Tapeout Schedule

By Vikas Gupta and Bhavani Prasad, Mentor Graphics Automated ECO fill helps you refill and re-verify late-stage changes quickly, while…

Will EUV Kill Multi-Patterning?

Will EUV Kill Multi-Patterning?

By David Abercrombie, Mentor Graphics Many people think EUV lithography means the end of multi-patterning. Do you?

Using Calibre eqDRC Verification Methodology for Curved Layouts in Silicon Photonics

Using Calibre eqDRC Verification Methodology for Curved Layouts in Silicon Photonics

Calibre eqDRC enables SiP designers to accurately verify non-Manhattan shapes in SiP designs.

Are You (Really) Ready for Your Next Node?

Are You (Really) Ready for Your Next Node?

By Michael White, Mentor Graphics Skipping nodes is gaining popularity, but it can bring some unexpected challenges. Are you prepared?

A new path for analog design constraints verification

A new path for analog design constraints verification

By Dina Medhat, Mentor Graphics Accurate verification of explicitly-defined analog design constraints is crucial for reliability and performance.

All Together Now: FOWLP in the Foundry

All Together Now: FOWLP in the Foundry

By John Ferguson, Mentor Graphics FOWLP design popularity is driving foundries to develop in-house FOWLP flows. How will that affect…

Fill/Cut Self-Aligned Double-Patterning

Fill/Cut Self-Aligned Double-Patterning

By David Abercrombie, Rehab Ali, Ahmed Hamed-Fatehy, and Shetha Nolke How the SID-SADP process affects your design decisions –