Calibre

Filter by:
Top-level schematic of a CMOS Low Dropout voltage regulator. An error amplifier (OA1) drives the gate of a PMOS pass transistor. The critical connection between the amplifier output and the transistor gate is labeled as the "VICTIM" net. The circuit also shows feedback resistors and an output capacitor.

Eliminating the silent killer of analog reliability: A structural approach to floating nets

October 12, 2026

By Bhanu Pandey, Product Engineer, Calibre Design Solutions A successful first silicon run starts with getting the design details right….

By Bhanu Pandey
5 MIN READ

Solving the extraction challenges of CFET and backside power

September 30, 2026

By Karen Chow, Sheetal Veronica, and Kunjesh Agashiwala Introduction: The vertical evolution of semiconductor architecture Both complementary field-effect transistor (CFET)…

By Karen Chow
12 MIN READ

Automated common resistance checking…it’s the smart thing to do!

January 30, 2023

By Hossam Sarhan Work smarter, not harder. Isn’t that what everyone is always telling you? Of course, it’s excellent advice,…

By Calibre IC Design & Manufacturing
< 1 MIN READ

TSMC OIP Ecosystem Forum 2022 all wrapped up, but not gone yet…

November 17, 2022

By Calibre Design Staff 1500+ attendees! 50 technical papers (30 live, 20 online) in three separate tracks! Standing room only…

By Calibre IC Design & Manufacturing
3 MIN READ

A touchy subject: RF IC layout verification

May 24, 2022

By Neel Natekar Radio frequency (RF) circuitry is an essential component of many of the critical applications we now rely…

By Calibre IC Design & Manufacturing
2 MIN READ

SAMP series finishes with SAMP cut mask decomposition techniques

September 9, 2020

By David Abercrombie and Rehab Kotb Ali – Mentor, A Siemens Business We’ve been writing about self-aligned multi-patterning (SAMP) topics…

By Calibre IC Design & Manufacturing
2 MIN READ
ECO Fill Can Rescue Your SoC Tapeout Schedule

ECO Fill Can Rescue Your SoC Tapeout Schedule

February 27, 2017

By Vikas Gupta and Bhavani Prasad, Mentor Graphics Automated ECO fill helps you refill and re-verify late-stage changes quickly, while…

By Calibre IC Design & Manufacturing
5 MIN READ
Will EUV Kill Multi-Patterning?

Will EUV Kill Multi-Patterning?

January 25, 2017

By David Abercrombie, Mentor Graphics Many people think EUV lithography means the end of multi-patterning. Do you?

By Calibre IC Design & Manufacturing
8 MIN READ
Using Calibre eqDRC Verification Methodology for Curved Layouts in Silicon Photonics

Using Calibre eqDRC Verification Methodology for Curved Layouts in Silicon Photonics

January 16, 2017

Calibre eqDRC enables SiP designers to accurately verify non-Manhattan shapes in SiP designs.

By Calibre IC Design & Manufacturing
< 1 MIN READ