Creating An Accurate FEOL CMP Model

By Ruben Ghulghazaryan, Jeff Wilson, and Ahmed AbouZeid FEOL CMP modeling helps designers and foundries…

Transistor level ESD verification in large SoC designs

Dina Medhat, Mentor Graphics ESD protection is critical, but difficult to verify. Using voltage propagation…

Context-Aware Latch-up Checking

By Matthew Hogan, Mentor Graphics Latch-up detection is challenging. Learn how automated LUP checks help…

The Pitfalls of Auto-Stitching in Double-Patterning

By David Abercrombie, Mentor Graphics Untimely DP stitching can cause more problems than it solves,…

Established Technology Nodes: The Most Popular Kid at the Dance

By Michael White, Mentor Graphics Established nodes have a lot of dancing left to do!…

Back-annotating DFM enhancements to place & route tools

By James Paris, Mentor Graphics Back-annotation of DFM enhancements to P&R simplifies iterations as designers…

Device Pin-Specific Property Extraction For Layout Simulation

By Phil Brooks, Mentor Graphics Can you accurately extract device pin-specific properties without creating phantom…

Synthesis of Design Rules and Patterns

By Michael White, Mentor Graphics Integrating pattern matching with design verification and process development yields…

Leveraging Reliability-Focused Foundry Rule Decks

By Matthew Hogan, Mentor Graphics Using your foundry‚Äôs reliability rule deck early on lets you…